TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 177

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

(1) Acknowledge mode specification
(2) Number of transfer bits
(3) Serial clock
generates an additional clock pulse for an acknowledge signal when operating in the
master mode. In the transmitter mode during the clock pulse cycle, the SDA pin is
released in order to receive the acknowledge signal from the receiver. In the receiver
mode during the clock pulse cycle, the SDA pin is set to the low level in order to
generate the acknowledge signal.
not generate a clock pulse for the acknowledge signal when operating in the master
mode.
counted for the acknowledge signal. During the clock for the acknowledge signal, when
a received slave address matches to a slave address set to the I2CAR or a “GENERAL
CALL” is received, the SDA pin is set to low level generating an acknowledge signal.
“GENERAL CALL” is received, in the transmitter mode during the clock for the
acknowledge signal, the SDA pin is released in order to receive the acknowledge signal
from the receiver. In the receiver mode, the SDA pin is set to low level generating an
acknowledge signal.
for the acknowledge signal are not counter.
data.
bit transmissions are executed in 8 bits. Other than these <BC2:0> retain a specified
value.
a.
Set SBICR1<ACK> to 1 for operation in the acknowledge mode. The TMP93CS20
Set <ACK> to 0 for operation in the non-acknowledge mode. The TMP93CS20 does
In the acknowledgment mode, when the TMP93CS20 is the slave mode, clocks are
After a received slave address matches to a slave address set to the I2CAR and a
In the non-acknowledgment mode, when the TMP93CS20 is the slave mode, clocks
SBICR1<BC2:0> are used to select a number of bits for transmitting and receiving
Since <BC2:0> are cleared to 000 as a start condition, a slave address and direction
Clock source
the SCL pin in the master mode. Set the baud rates, which have been calculated
according to the formula below, to meet the specifications of the I
the smallest pulse width of t
t
t
fscl = 1/(t
LOW
HIGH
SBICR1<SCK2:0> are used to select a maximum transfer frequency output on
=
= 2
t
= 2
2 × 2
HIGH
n
LOW
n
/f
f
/f
FPH
FPH
FPH
n
+ 12
+ t
+ 12/f
HIGH
Figure 3.10.7 Clock Source
t
LOW
FPH
)
93CS20-175
(Bits 2 to 0 in the SBICR1)
LOW
<SCK2:0>
.
1/fscl
000
001
010
011
100
101
110
10
n
4
5
6
7
8
9
2
C bus, such as
TMP93CS20
2004-02-10