TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 42

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TMP93xy20FG

Manufacturer Part Number
TMP93xy20FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP93xy20FG

Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M/P
Rom Combinations
64
Ram Combinations
2
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
-
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
4
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
-
Dual Clock
Y
Number Of I/o Ports
88
Power Supply Voltage(v)
4.5 to 5.5
(2) Register configuration (CPU control registers)
These control registers can only be set with the “LDC cr, r” instruction.
Example:
Channel 0
Channel 1
Channel 2
Channel 3
DMAD0
DMAD1
DMAD2
DMAD3
DMAS0
DMAS1
DMAS2
DMAS3
32 bits
LD
LDC
LD
LDC
LD
LDC
LD
LDC
DMAC0
DMAC1
DMAC2
DMAC3
16 bits
XWA, 100H
DMAS0, XWA
XWA, 50H
DMAD0, XWA
WA, 40H
DMAC0, WA
A, 05H
DMAM0, A
DMAM0
DMAM1
DMAM2
DMAM3
8 bits
93CS20-40
Transfer source address register 0
Transfer destination address register 0
Transfer counter register 0
Transfer mode register 0
Transfer source address register 1
Transfer destination address register 1
Transfer counter register 1
Transfer mode register 1
Transfer source address register 2
Transfer destination address register 2
Transfer counter register 2
Transfer mode register 2
Transfer source address register 3
Transfer destination address register 3
Transfer counter register 3
Transfer mode register 3
(Use lower 24 bits.)
(1 to 65536)
TMP93CS20
2004-02-10

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