TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 93

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

3.
Timer registers
registers match the values of the corresponding up counters, the comparator match detect
signal becomes active. If the set value is 00H, this signal becomes active when the up
counter overflows.
example of the TREG2.
double buffer structure should be enabled or disabled. It is disabled when <TR2DE> = 0
and enabled when it is set to 1.
timer register when the 2
mode. Therefore, during timer mode, the double buffer cannot be used.
use the double buffer, write data in the timer register, set <TR2DE> to 1, and write the
following data in the register buffer.
Note: The timer register and the register buffer are allocated at the same memory address.
These are 8-bit registers for setting a time interval. When the values of the timer
Timer registers TREG0 and TREG2 have a double buffer. The following describes an
The 8-bit timer double buffer control register TRDC<TR2DE> bit controls whether the
In the double buffer enable state, the data set in the register buffer are transferred to the
Upon resetting, TRDC<TR2DE> will be initialized to 0, disabling the double buffer. To
Timer register 2 (TREG2)
When <TR2DE> = 0, the same value is written in the register buffer and in the timer
register, while when <TR2DE> = 1 the value is written only into the register buffer.
The memory address of each timer register is as follows.
Both of these registers are write only and cannot be read.
Comparator (CP2)
Internal data bus
Register buffer 2
Up counter
TREG0: 000022H
TREG1: 000023H
Figure 3.7.4 Configuration of Timer Register 2
Write
Shift trigger
n
− 1 overflow occurs in PWM mode, or at the PPG cycle in PPG
93CS20-91
TREG2: 000026H
TREG3: 000027H
TRDC<TR2DE>
Selector
Matching detection of PPG cycle
2
TREG2 WR
n
− 1 overflow of PWM
TMP93CS20
2004-02-10