TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 153

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TMP93xy20FG

Manufacturer Part Number
TMP93xy20FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP93xy20FG

Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M/P
Rom Combinations
64
Ram Combinations
2
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
-
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
4
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
-
Dual Clock
Y
Number Of I/o Ports
88
Power Supply Voltage(v)
4.5 to 5.5
System clock f
SCLK0
(Shared by P65)
SCLK0
(Shared by P65)
3.9
RXD0
(Shared by P64)
3.9.2
SC0MOD<RXE>
SYS
Configuration
φT0
φT2
φT8
φT32
RXDCLK
Figure 3.9.14 shows the block diagram of the serial channel 0.
(φ1)
Serial clock generation circuit
I/O interface mode
RB8
BR0CR<BR0CK1:0>
Receive counter
Receive buffer 1 (Shift register)
(UART only ÷ 16)
Receive control
Receive buffer 2 (SC0BUF)
Baud rate generator
Figure 3.9.14 Block Diagram of the Serial Channel 0
<BR0S3:0>
BR0CR
<BR0ADD>
BR0CR
SC0MOD
<BR0K3:0>
<WU>
BRADD0
<OERR> <PERR> <FERR>
÷2
93CS20-151
INTRX0
<PE>
interrupt control
Serial channel
Parity control
Internal data bus
TO0TRG
(Timer 0 comparator output)
Error flag
SC0CR
SC0CR
SC0MOD
<SC1:0>
SC0CR
<IOC>
<EVEN>
INTTX0
I/O interface mode
UART
mode
SC0MOD
<SM1:0>
TXDCLK
TB8
(UART only ÷ 16)
Transmission
Transmission buffer (SC0BUF)
Transmission
SIOCLK
control
counter
SC0MOD<CTSE>
TMP93CS20
2004-02-10
(Shared by P63)
(Shared by P65)
TXD0
CTS0

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