TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 116

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

T16CR
(003AH)
Bit symbol
Read/Write
After reset
Function
Note 1: In case of not using the 7 stage binary counter as a warm-up timer, a stable clock signal must be input from
Note 2: T16CR<Bit6> is always read as 1.
an external circuit.
Warm-up
timer
control
QCU
R/W
Figure 3.8.7 Registers for 16-Bit Timer/Event Counter (5/6)
7
0
6
16-Bit Timer Countrol Register
Prescaler and timer
run/stop control
0: Stop and clear
1: Run (Count up)
TARUN
5
0
93CS20-114
T8RUN
4
0
Double buffer control
Count operation
Warm-up timer input control
DBAEN: Double buffer of TREGA
DB8EN: Double buffer of TREG8
DB6EN: Double buffer of TREG6
DB4EN: Double buffer of TREG4
TARUN: 16-bit timer (Timer A)
T8RUN: 16-bit timer (Timer 8)
Double
buffer of
TREGA
0
1
0
1
0
1
DBAEN
3
0
Disable
Enable
Stop and clear
Count
Uses 7 stage binary counter
Does not use 7 stage binary counter (Note 1)
R/W
Double
buffer of
TREG8
DB8EN
Double buffer
0: Disable
1: Enable
2
0
Double
buffer of
TREG6
DB6EN
1
0
Double
buffer of
TREG4
TMP93CS20
DB4EN
2004-02-10
0
0