TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 205

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

XT1
X1
3.12 Watchdog Timer (Runaway detection timer) and Warm-up Timer
3.12.1
fs
the CPU has started to malfunction (Runaway) due to causes such as noise. When the watchdog
timer detects a malfunction, it generates a INTWD interrupt (Non-maskable) to notify the CPU
of the malfunction.
This is used for releasing stop and also before changing the system clock.
fc/fs changing warm-up clock
÷2
The TMP93CS20 contains a watchdog timer for runaway detection.
The watchdog timer (WDT) is used to return the CPU to a normal state when it detects that
Using the malfunction detected result forces a reset.
The watchdog timer consists of 7-stage and 15-stage binary counters.
These binary counters are also used as a warm-up timer for internal oscillator stabilization.
Configuration
timer.
÷4
Figure 3.12.1 shows the block diagram for the watchdog timer (WDT) and warm-up
÷2
÷8
Figure 3.12.1 Block Diagram for Watchdog Timer/Warm-up Timer
÷16
Selection of WDT and warm-up clock
SYSCR1<GEAR2:0>
T16CR<QCU>
WDMOD<WARM>
7-stage
counter
SYSCR0<WUEF>
binary
SYSCR1<SYSCK>
÷2
93CS20-203
2
Internal reset
15-stage binary counter
7
Selector
CPU
2
9
Interrupt
2
control
Selector
11
2
13
2
15
Reset
Enable
SYSCR0<WUEF>
WDMOD
<WDTP1:0>
HALT instruction
(STOP, IDLE1 mode)
Q S
R
Reset
WDMOD<RESCR>
WDTI interrupt
RESET
Reset
WDMOD<WDTE>
Write disable code to
WDCR (B1H)
Write clear code to
WDCR (4EH)
TMP93CS20
2004-02-10