TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 86

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

Note 1: Access priority is highest for built-in I/O, then built-in memory, and lowest for the chip select/wait
Note 2: External areas other than WAITC0 to WAITC2 are accessed in 0 WAIT mode.
3.6.3
controller.
When using the chip select/wait controller, do not specify the same address area more than once.
(However, when specifications overlap, only one of them will be utilized. For example, when
addresses 7F00H to 7FFFH for WAITC0 are specified at the same time as 8A0H to 7FFFH for
WAITC1, only the WAITC0 setting and pin will be active.)
Bus Width/Wait Control
Out of the whole memory area, address areas that can be specified are divided into four
parts. Addresses from 000000H to 3FFFFFH are further divided as follows: 7F00H to
7FFFH is specified for WAITC0; 8A0H to 7FFFH, for WAITC1; and 8000H to 3FFFFFH,
for WAITC2. The reason is that a device other than ROM (e.g., RAM or I/O) might be
connected externally.
expansions to external I/O.
possible extensions to external RAM.
possible extensions to external ROM. After resetting, WAITC2 is enabled in a 16-bit bus
and 2-wait configuration. With the TMP93CS20, which does have a built-in ROM,
addresses from FF0000H to FFFFFFH are used as the internal ROM area; WAITC2 is
disabled in this area. After resetting, the CPU reads the program from the built-in ROM in
16-bit bus, 0 WAIT mode.
An image of the actual addresses which can be specified by chip select is shown below.
7F00H to 7FFFH (256 bytes) designated as WAITC0 are mapped mainly for possible
8A0H to 7FFFH (Approx. 30 Kbytes) designated as WAITC1 are mapped mainly for
8000H to 3FFFFFH (Approx. 4 Mbytes) designated as WAITC2 are mapped mainly for
FFFFFFH
C00000H
000000H
400000H
800000H
7F00H
8000H
<B0C1:0> = “00”
<B0C1:0> = “01”
<B0C1:0> = “10”
<B0C1:0> = “11”
(Mainly for I/O)
WAITC0
93CS20-84
8A0H
(Mainly for RAM)
<B1C1:0> = “00”
<B1C1:0> = “01”
<B1C1:0> = “10”
<B1C1:0> = “11”
WAITC1
(Mainly for ROM)
<B2C1:0> = “00”
<B2C1:0> = “01”
<B2C1:0> = “10”
<B2C1:0> = “11”
WAITC2
TMP93CS20
2004-02-10