TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 252

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

Symbol
ADMOD0
ADMOD1
AD
REG04L
AD
REG04H
AD
REG15L
AD
REG15H
AD
REG26L
AD
REG26H
AD
REG37L
AD
REG37H
(10) AD converter control
AD
mode
control
register 0
AD
mode
control
register 1
AD
conversion
result
register
0/4 low
AD
conversion
result
register
0/4 high
AD
conversion
result
register
1/5 Low
AD
conversion
result
register
1/5 high
AD
conversion
result
register
2/6 Low
AD
conversion
result
register
2/6 high
AD
conversion
result
register
3/7 low
AD
conversion
result
register
3/7 high
Name
Bits 5 to 1 are always read as 1.
Bit0 is the AD conversion result storage flag <ADRxRF>. Bit0 is set to
1 when the conversion result is stored, and it is cleared by reading
either ADREGxH or ADREGxL.
Address
5EH
5FH
60H
61H
62H
63H
64H
65H
66H
67H
0: Not end
1: End
0: OFF
1: ON
AD
conversion
VREF control
VREFON
ADR01
ADR09
ADR11
ADR19
ADR21
ADR29
ADR31
ADR39
EOCF
R/W
7
0
1
Undefined
Undefined
Undefined
Undefined
R
R
R
R
R
0: Not busy
1: Busy
AD
conversion
busy flag
ADR00
ADR08
ADR10
ADR18
ADR20
ADR28
ADR30
ADR38
ADBF
6
0
Always fixed
to “0”.
Converted data for channel X
Lower 2 bits of AD result are stored
Lower 2 bits of AD result are stored
Lower 2 bits of AD result are stored
Lower 2 bits of AD result are stored
93CS20-250
ADR07
ADR17
ADR27
ADR37
－
5
0
Upper 8 bits of AD result are stored
Upper 8 bits of AD result are stored
Upper 8 bits of AD result are stored
Upper 8 bits of AD result are stored
Always fixed
to “0”.
ADR06
ADR16
ADR26
ADR36
－
4
0
Undefined
Undefined
Undefined
Undefined
R
R
R
R
0: Each 1
1: Each 4
0: Disable
1: Enable
AD
conversion
interrupt in
fixed
channel
repeat mode
External
trigger start
control
ADTRGE
time
times
ADR05
ADR15
ADR25
ADR35
ITM0
7 6 5 4 3 2 1 0
3
9 8 7 6 5 4 3 2 1 0
0
0
R/W
ADREGxH
0: Single
1: Repeat
Repeat
mode
REPET
ADCH2
mode
mode
ADR04
ADR14
ADR24
ADR34
Analog input channel selection
2
0
0
R/W
0: Fixed
1: Channel
Scan mode
ADCH1
channel
mode
scan mode
ADR03
ADR13
ADR23
ADR33
SCAN
7 6 5 4 3 2 1 0
1
0
0
TMP93CS20
ADREGxL
2004-02-10
0: Don't Care
1: Start
AD
conversion
start
Always “0”
when data is
read.
AD conversion
result storage
flag
AD conversion
result storage
flag
AD conversion
result storage
flag
AD conversion
result storage
flag
ADR0RF
ADR1RF
ADR2RF
ADR3RF
ADCH0
ADR02
ADR12
ADR22
ADR32
ADS
0
R
R
R
R
0
0
0
0
0
0