TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 48

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

Read-
modify-
write is
prohibited
IIMC
(007BH)
Bit symbol
Read/Write
After reset
Function
Note 1: This is a case of changing from level-sence to edge-sence for INT0 pin mode. (Changing from 1 to 0 for
Note 2: See electrical characteristics in section 4 for external interrupt input pulse.
(2) External interrupt control
<IOIE>.)
Execution example:
0:
1:
LD
LD
LD
INT7
rising
edge
INT7
falling
edge
I7FE
7
0
Figure 3.4.7 Interrupt Input Mode Control Register
(INTE0AD), XXXX0000B
(IIMC), XXXXX10XB
(INTE0AD), XXXX0nnnB
0: INT4
1: INT4
rising
edge
falling
edge
I4FE
6
0
Interrupt Input Mode Control Register
0: INT3
1: INT3
rising
edge
falling
edge
I3FE
5
0
93CS20-46
0: INT2
1: INT2
rising
edge
falling
edge
I2FE
;
;
;
4
0
INT0 disable, clear the request flag.
Change from level to edge.
Set interrupt level “n” for INT0, clear the request flag.
W
0: INT1
1: INT1
rising
edge
falling
edge
I1FE
3
0
NMI
INT0 level enable (Note 1)
0
1
0
1
0: INT0
1: INT0
rising edge enable
rising
edge
falling
edge
I0FE
2
0
Interrupt request generation at falling
edge
Interrupt request generation at rising
and falling edge
Rising edge detect interrupt
High level interrupt
0: INT0
1: INT0
edge-
sense
mode
level-
sense
mode
I0LE
1
0
1: Can be
NMIREE
accept
ed in
rising
edge.
NMI
TMP93CS20
0
0
2004-02-10