TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 127

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

T8MOD
(0038H)
Bit symbol
Read/Write
After reset
Function
Figure 3.8.15 Registers for 16-Bit Timer/Event Counter (1/4)
7
6
Timer 8 Mode Control Register
Control of
software
capture
0: Software
1: Don’t care
CAP8IN
capture
W
5
1
93CS20-125
Capture timing
00: Disable INT8 occurs
01: TI8↑
10: TI8↑
11: TFF1↑ TFF1↓
CAP89M1
at rising edge.
INT8 occurs at
rising edge.
INT8 occurs at
falling edge.
INT8 occurs at
rising edge.
4
0
Timer 8 input clock
Clearing the up counter UC8
Capture timing of timer 8
Software capture
TI9↑
TI8↓
00
01
10
11
00
01
10
11
CAP89M0
0
1
0
1
3
0
Capture disable
CAP8 at TI8 rise
CAP9 at TI9 rise
CAP8 at TI8 rise
CAP9 at TI8 fall
CAP8 at TFF1 rise
CAP9 at TFF1 fall
External clock (TI8)
φT1
φT4
φT16
Clear disable
Clear by match with TREG9
The up counter 8 value is loaded to CAP8
Don’t care
Capture control
Control of
timer 8
0: Clear
1: Clear
disable
enable
CLE
R/W
2
0
Timer 8 source clock
00: TI8
01: φT1
10: φT4
11: φT16
Interrupt occurs at
the rising edge of
TI8 (INT8) input.
Interrupt occurs at
the faling edge of
TI8 (INT8) input.
Interrupt occurs at
the rising edge of
TI8 (INT8) input.
T8CLK1
1
0
INT8 control
TMP93CS20
T8CLK0
2004-02-10
0
0