TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 184

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

SCL pin
SDA pin
SCL pin
SDA pin
<PIN>
INTS2
interrupt request
<PIN>
INTS2
interrupt request
Figure 3.10.14 Example of when <BC2:0> = 000, <ACK> = 1 (Receiver mode)
When <TRX> is 0 (Receiver mode)
Figure 3.10.15 Termination of Data Transfer in Master Receiver Mode
Set <ACK> to 1 and read the received data from the SBIDBR to release the SCL
line. The read data is undefined immediately after the slave address is set.) After
the data is read, <PIN> becomes 1. Serial clock pulse for transferring new 1 word of
data is defined SCL and outputs “L” level from SDA pin with acknowledge timing.
set to the low level. The TMP93CS20 outputs a clock pulse for one-word of data
transfer and the acknowledge signal each time that received data is read from the
SBIDBR.
before reading data which is one-word before the last data to be received. The last
data does not generate a clock pulse for the acknowledge signal. After the data is
transmitted and an interrupt request has occurred, set <BC2:0> to 001 and read
the data. The TMP93CS20 generates a clock pulse for a 1-bit data transfer. Since
the master device is a receiver, the SDA line of the bus keeps the high level. The
transmitter receives the high-level signal as the ACK signal. The receiver indicates
to the transmitter that data transfer is complete.
TMP93CS20 generates the stop condition and terminates data transfer.
Read SBIDBR
D7
D7
When the next transmitted data is other than 8 bits, set SBICR1<BC2:0> again.
The INTS2 interrupt request then occurs and <PIN> becomes 0. The SCL pin is
In order to terminate the transmitting data to the transmitter, set <ACK> to 0
After 1-bit data is received and the interrupt request has occurred, the
1
1
0 → <ACK>
Read SBIDBR
D6
D6
2
2
D5
D5
3
3
93CS20-182
D4
D4
4
4
D3
D3
5
5
D2
D2
6
6
Output of Master
Output of Slave
D1
D1
7
7
D0
D0
8
8
1
Acknowledge signal
sent to a transmitter
001 → <BC2:0>
Read SBIDBR
9
Acknowledge signal
to a transmitter
TMP93CS20
New D7
2004-02-10