TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 158

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TMP93xy20FG

Manufacturer Part Number
TMP93xy20FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP93xy20FG

Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M/P
Rom Combinations
64
Ram Combinations
2
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
-
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
4
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
-
Dual Clock
Y
Number Of I/o Ports
88
Power Supply Voltage(v)
4.5 to 5.5
TREG0
12.288000
14.745600
fc [MHz]
9.830400
10H
14H
1H
2H
3H
4H
5H
8H
AH
Note 1: Transfer rates in I/O interface mode are 8 times faster than the values given in the above table.
Note 2: This table is calculated when fc is selected as a system clock, the clock gear is set for fc, and the system
Note 1: Timer 0 match detect signal cannot be used as the transfer clock in I/O interface mode.
Note 2: This table is calculated when fc is selected as a system clock, the clock gear is set for fc, and system clock
Table 3.9.3 Selection of Transfer Rate (when timer 0 with input clock φT1 is used)
Table 3.9.2 Selection of Transfer Rate (when baud rate generator is used)
fc
clock as the prescaler clock input.
as the prescaler clock input.
How to calculate the transfer rate (when timer 0 is used):
Transfer rate
Frequency
Divisor
12.288 MHz
96
48
32
24
19.2
12
Input Clock
9.6
6
4.8
A
C
2
4
8
0
5
3
6
=
The clock frequency selected by the register SYSCR0<PRCK1:0>
12 MHz
76.800
38.400
19.200
38.400
19.200
76.800
38.400
19.200
φT0
31.25
9.600
93CS20-156
9.8304 MHz
TREG0 × 8 × 16
19.200
19.200
φT2
9.600
4.800
2.400
9.600
4.800
9.600
4.800
76.8
38.4
19.2
9.6
4.8
(when Timer 0 (input clock φT1) is used)
8 MHz
φT8
4.800
2.400
1.200
0.600
2.400
1.200
4.800
2.400
1.200
62.5
31.25
6.144 MHz
φT32
Unit (Kbps)
1.200
0.600
0.300
0.150
0.600
0.300
1.200
0.600
0.300
Unit (Kbps)
48
24
16
12
TMP93CS20
9.6
6
4.8
3
2.4
2004-02-10

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