TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 254

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

6.
Port Section Equivalent Circuit Diagram
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■
■
•
•
P0 (AD0 to AD7), P1 (AD8 to AD15, A8 to A15), P67 (TO1)
P30 (
P2 (A16 to A23, A0 to A7), P32 (
Reading the circuit diagram
The input protection resistance ranges from several tens of ohms to several hundreds of
ohms.
logic IC [74HCXX] series.
Output enable
Basically, the gate symbols written are the same as those used for the standard CMOS
The dedicated signal is described below.
Output enable
Stop: This signal becomes active 1 when the HALT mode setting register is set to the
Output data
RD
Output data
Input data
Input data
), P31 (
STOP
STOP
Stop mode and the CPU executes the HALT instruction. When the drive enable
bit [DRVE] is set to 1, however, stop remains at 0.
Output data
WR
)
STOP
Input enable
Input enable
93CS20-252
HWR
), P72 (TO8), P73 (SCOUT), P76 (TOA)
VCC
VCC
P-ch
N-ch
VCC
VCC
Programmable
pull-up resistance
I/O
Output
I/O
TMP93CS20
2004-02-10