TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 34

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

3.4.1
General-purpose Interrupt Processing
interrupts or interrupts generated by the CPU because of attempts to execute illegal
instructions, the following steps (1) and (3) are not executed.
(1) The CPU reads the interrupt vector from the interrupt controller. When more than one
(2) The CPU pushes the program counter and the status register to the system stack area
(3) The CPU sets a value in the CPU interrupt mask register <IFF2:0> that is higher by 1
(4) The CPU increments the interrupt nesting counter (INTNEST).
(5) The CPU jumps to an address stored in the FFFF00H + interrupt vector, then starts
above.
this instruction restores the contents of the program counter and the status registers, and
decrements the interrupt nesting counter (INTNEST).
acceptance of maskable interrupts can. A priority can be set for each source of maskable
interrupts. The CPU accepts any interrupt request with a priority higher than the current
value in the CPU mask register <IFF2:0>. The CPU mask register <IFF2:0> is then set to a
value higher by 1 than the priority of the accepted interrupt. Thus, if another interrupt is
generated with a priority level higher than the interrupt currently being processed, the
CPU accepts the interrupt with the higher level, causing interrupt processing to nest.
generated during the time that CPU is processing the above steps (1) to (5), and is accepted
before the first instruction in the interrupt processing routine is executed, this will cause
interrupt processing to nest. (The nesting process is the same as in the case of overlapping
each non-maskable interrupt (Level 7).) The CPU does not accept an interrupt request of
the same priority level as that of the interrupt currently being processed.
acceptance of all maskable interrupts is disabled.
When accepting an interrupt, the CPU operates as follows. In the cases of software
The following table shows the number of processing states corresponding to steps 1 to 5
The RETI instruction is usually used to complete the interrupt processing. Executing
Though acceptance of non-maskable interrupts cannot be disabled by programming,
If an interrupt request with a priority higher than the currently-processed interrupt is
Resetting initializes the CPU mask registers <IFF2:0> to the value 7, therefore,
The following (1) to (5) show a flowchart of interrupt processing.
Bus Width of
interrupt with the same priority level is generated simultaneously, the interrupt
controller generates interrupt vectors in accordance with the default priority, then
clears the interrupt request. The default priority is fixed as follows: the smaller the
vector value, the higher the priority.
(Area indicated by the system mode stack pointer (XSP)).
than the priority level value of the accepted interrupt. However, if the accepted
interrupt’s priority value is 7, 7 is set without an increment.
the interrupt processing routine.
Stack Area
16 bits
8 bits
Bus Width of Interrupt
Vector Area
16 bits
16 bits
8 bits
8 bits
93CS20-32
Number of Interrupt
Processing States
35
31
29
25
TMP93CS20
2004-02-10