TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 195

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

Analog
input
3.11 Analog/Digital Converter
ADTRG
Note 1: When the power supply current is reduced in IDLE2, IDLE1, STOP mode, there is possible to set a
Note 2: In regard to the lowest operation frequency
AN7 (P57)
AN6 (P56)
AN5 (P55)
AN4 (P54)
AN3 (P53)
AN2 (P52)
AN1 (P51)
AN0 (P50)
(P37)
converter) with 8-channel analog input.
AN7) are also used as input only port 5 and can be also used as input ports.
VREFH
VREFL
standby enabling the internal comparator due to a timing. Stop operation of AD converter before
execution of HALT instruction.
The operation of AD converter is guaranteed with clock of f
guaranteed with fs clock.
TMP93CS20 incorporate a high-speed, high-precision 10-bit analog/digital converter (AD
Figure 3.11.1 is a block diagram of the AD converter. The 8-channel analog input pins (AN0 to
ADMOD1
<ADCH2:0>
Multiplexer
Figure 3.11.1 Block Diagram of AD Converter
ADTRG
Decoder
<VREFON>
<ADTRGE>
93CS20-193
<EOCF> <ADBF> <ITM0> <REPET> <SCAN> <ADS>
ADMOD0
Channel select
Sample
End
hold
Internal data bus
Busy
Interrupt
FPH
DA converter
control circuit
Repeat
AD converter
≥ 4 MHz (Used fc clock), but not
Scan
Start
ADREG04H to 37H
ADREG04L to 37L
AD conversion
result register
ADTRG
INTAD
interrupt
TMP93CS20
2004-02-10