TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 227

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TMP93xy20FG

Manufacturer Part Number
TMP93xy20FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP93xy20FG

Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M/P
Rom Combinations
64
Ram Combinations
2
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
-
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
4
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
-
Dual Clock
Y
Number Of I/o Ports
88
Power Supply Voltage(v)
4.5 to 5.5
Note: Since the CPU accesses the internal area to read data from a port, the control signals of external
(1) Read cycle
Port input
X1/XT1
CLK
A0 to A23
AD0 to AD15
ALE
RD
WAIT
pins such as
regarded as depicting internal operation. Please also note that the timing and AC characteristics
of port input/output shown above are typical representation. For details, contact your local
Toshiba sales representative.
(Note)
RD
t
AK
and
t
OSC
t
LL
CS
t
AL
t
ACH
A0 to A15
are not enabled. Therefore, the above waveform diagram should be
t
t
ACL
APH
t
AWH
t
t
93CS20-225
LC
LA
t
AWL
t
APH2
t
CLK
t
ADH
t
RD
t
ADL
t
t
CW
RR
t
KA
D0 to D15
t
t
HR
t
CA
CL
t
TMP93CS20
RAE
2004-02-10

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