TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 103

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

TREG2, when the up counter UC2 is not to be cleared.
when the up counter UC3 and TREG3 values are found to match. When the match detect
signal is output simultaneously from the comparators of both timer 2 and timer 3, the up
counters UC2 and UC3 are cleared to 0, and the interrupt INTT3 is generated. If inversion
is enabled, the value of the timer flip-flop TFF3 is inverted.
(3) 8-bit PPG (Programmable pulse generation) output mode
The comparator signal is output from timer 2 each time the up-counter UC2 matches
With the timer 3 comparator, the match detect signal is output at each comparator check
Example:
TREG2 and UC2 match
(Interrupt INTT0)
TREG3 and UC2 match
(Interrupt INTT3)
The output pulse may be either low-active or high-active. In this mode, timer 1 or timer
3 cannot be used.
as P83).
output each time the 8-bit up counter (UC2) matches the timer registers TREG2 and
TREG3.
TREG3.
for counting by setting TRUN<T3RUN>to 1.
Square wave pulse can be generated at any frequency and duty by timer 0 or timer 2.
Timer 0 outputs a pulse to the TO1 pin (also used as P67), or the TO3 pin (also used
The operation of timer 2 will be explained below.
In this mode, a programmable square wave is generated by inverting the timer
However, it is necessary for the set value of TREG2 to be smaller than that of
Though the up counter (UC3) of timer 3 is not used in this mode, UC3 should be set
Figure 3.7.14 shows the block diagram for this mode.
Value of up counter
(UC3, UC2)
Timer 2 comparator
match detect signal
Interrupt INTT3
Timer output TO3
When TREG3 = 04H and TREG2 = 80H
Figure 3.7.12 Timer Output by 16-Bit Timer Mode
Figure 3.7.13 8-Bit PPG Output Waveforms
TO3
0000H
93CS20-101
0080H
t
H
0180H
t
TREG2
t
L
TREG3
0280H
0380H
0480H
Inversion
TMP93CS20
2004-02-10