TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 102

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

(2) 16-bit timer mode
as a pair.
timer 1 to 01 establishes a 16-bit timer mode.
the input clocks of timer 1 and timer 3, regardless of the set value of T10MOD<T1CLK1:0>
or T32MOD<T3CLK1:0>. Table 3.7 (1) shows the selection of timer 0 and timer 2 input
clocks.
TREG2, and the upper 8 bits are set by TREG1 and TREG3. Note that TREG0 or TREG2
always must be set first. (Writing data into TREG0 or TREG2 disables the comparator
temporarily, and the comparator is restarted by writing data into TREG1 or TREG3.)
3.
Setting example:
A 16-bit interval timer is configured by using timer 0 and timer 1 or timer 2 and timer 3
Setting timer mode register T10MOD<T10M1:0> or T32MOD<T32M1:0> of timer 0 and
When set in 16-bit timer mode, the overflow outputs of timer 0 and timer 2 will become
The lower 8 bits of the timer (Interrupt) cycle are set by the timer registers TREG0 and
Making timer 1 count up by matching the signal from the timer 0 comparator.
(Same function is achieved by using timer 3 and timer 2.)
to timer 1.
Comparator output
(Timer 0 match)
Timer 0 up counter
(when TREG0 = 5)
Timer 1 up counter
(when TREG1 = 2)
Timer 1 matching output
Set the 8-bit timer mode, and set the comparator output of timer 0 as the input clock
Figure 3.7.11 Timer 1 Count-up Regulated by Timer 0
*
When counting with the φT16 input clock (6.4 µs at 20 MHz)
Therefore, set TREG3 = F4H and TREG2 = 24H, respectively.
To generate an interrupt INTT3 every 0.4 seconds at fc = 20 MHz, set the following values for timer
registers TREG2 and TREG3.
Clock condition
0.4 s ÷ 6.4 µs = 62500 = F424H
1
93CS20-100
2
3
1
4
System clock:
Clock gear:
Prescaler clock: f
5
1
2
High frequency (fc)
1 (fc)
FPH
3
2
4
5
1
2
TMP93CS20
1
2004-02-10
3