TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 119

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

(2) Up counter
(3) Timer registers
prescaler. This selection is made by prescaler clock selection register SYSCR0
<PRCK1:0>.
prescaler outputs.
TRUN<PRRUN>. Counting starts when <PRRUN> is set to 1. The prescaler is cleared
to 0 and stops operation when <PRRUN> is set to 0.
TRUN<PRRUN> to 0 to reduce the power consumption of the prescaler before the
HALT instruction is executed.
clock specified by T4MOD<T4CLK1:0> register.
φT1, φT4, and φT16 from the 9-bit prescaler (which is also used as an 8-bit timer), as
will as the external clock from the TI4 pin (which itself can also be used as the P40 or
KEY0 pin). When reset, <T4CLK1:0> will be initialized to 00; this selects TI4 input
mode. Counting or stop and clear of the counter are controlled by timer operation
control register TRUN<T4RUN>.
timer register TREG5. The “clear enable/disable” setting is made by T4MOD<CLE>.
counter UC4 matches the value set in this timer register, the comparator match detect
signal will be activated.
always needed. For example, either by using a 2-byte data transfer instruction, or by
using 1-byte data transfer instructions twice: once for the lower 8 bits and once for the
upper 8 bits in that order.
The clock selected from among f
Resetting sets <PRCK1:0> to 00, selecting the f
The 16-bit timers 4 and 6 select among 3 clock inputs: φT1, φT4, and φT16 among the
This prescaler can be run or stopped by the timer operation control register
Resetting clears <PRRUN> to 0 and stops the prescaler.
When the IDLE1 mode (in which only the oscillator operates) is used, set
The up counter is a 16-bit binary counter which counts up according to the input
The alternatives for selecting the input clock include any one of the internal clocks
When clearing is enabled, up counter UC4 will be cleared each time it matches the
If clearing is disabled, the counter operates as a free-running counter.
When an overflow of UC4 occurs, the interrupt request INTTO4 occurs.
These two 16-bit registers are used to set the interval time. When the value of up
Setting data in the both upper and lower timer registers TREG4 and TREG5 is
TREG4 to TREG7 can not be read out, because they are write only registers.
Timer 4
Timer 6
Upper 8 bits
Upper 8 bits
(TREG4H)
(TREG6H)
00002BH
00003CH
TREG4
TREG6
Lower 8 bits
Lower 8 bits
(TREG4L)
(TREG6L)
00002AH
00003BH
93CS20-117
FPH
, fc/16, and fs is divided by 4 and input to this
Upper 8 bits
Upper 8 bits
(TREG5H)
(TREG7H)
00002DH
00003EH
FPH
clock input divided by 4.
TREG5
TREG7
Lower 8 bits
Lower 8 bits
(TREG5L)
(TREG7L)
00002CH
00003DH
TMP93CS20
2004-02-10