TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 10

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

3.
3.1
3.1.1
Operation
also refer to section 7., “Points to Note and Restrictions”, which describes some points requiring
careful attention.
This section describes in blocks the functions and basic operations of TMP93CS20 device. Please
CPU
the CPU operation, see the information on the TLCS-900/L CPU in the previous chapter).
in the previous chapter, entitled TLCS-900/L CPU.
TMP93CS20 devices have a built-in high-performance 16-bit CPU (900/L CPU). (For basics of
This section describes some CPU functions unique to the TMP93CS20, that are not described
Reset
within the operating voltage range, and that the internal high-frequency oscillator has
stabilized. Then set the
MHz). Thus, when turn on the switch, be set to the power supply voltage is within the
operating voltage range, and that the internal high-frequency oscillator has stabilized.
Then hold the
mode f
•
•
•
•
•
reset makes no changes in any CPU internal registers other than those specifically
mentioned above.
pins is affected as follows:
•
•
•
•
Note 2: The CLK pin is pulled up to “H” level during reset. When the voltage is put down
Note 1: Resetting makes no change in any register in the CPU except the program counter (PC),
When resetting the TMP93CS20 microcontroller, ensure that the power supply voltage is
Clock gear is initialized 1/16 mode by reset operation. It means that the system clock
When a reset signal is accepted, the CPU sets itself as follows:
When the reset is released, instruction execution starts from PC (the reset vector). The
When a reset is received, signal and data processing for built-in I/Os, ports, and other
Figure 3.1.1 shows the reset timing chart of TMP93CS20.
The program counter (PC) is set according to the reset vector that is stored from
FFFF00H to FFFF02H.
The stack pointer (XSP) for system mode is set to 100H.
The <IFF2:0> bits of the status register SR are set to 111. (Sets mask register to
interrupt level 7.)
The <MAX> bit of SR is set to 1. (Sets to maximum mode. See previous chapter.)
The <RFP2:0> bits of SR are set to 000. (Clears register banks to 0.)
Initializes built-in I/O registers as per specifications.
Sets port pins (including pins also used as built-in I/Os) to general-purpose
input/output port mode.
Pulls up the CLK pin to 1.
Sets the ALE pin to high impedance (High-Z).
PC<7:0>
PC<15:8> ←
PC<23:16> ←
SYS
status register (SR), and stack pointer (XSP), nor in the data in the internal RAM.
externally, there is possible to cause malfunctions.
is set to fc/32 (= fc/16 × 1/2).
RESET
←
input to low level at least for 10 system clocks.
Data in location FFFF00H
Data in location FFFF01H
Data in location FFFF02H
RESET
input to low level at least for 10 system clocks (16 µs at 20
93CS20-8
TMP93CS20
2004-02-10