TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 24

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

CPU
I/O Port
8-bit timer
16-bit timer
Timer for realtime clock
Serial channel
Serial bus interface controller
AD converter
Watchdog timer
Interrupt controller
WDMOD<HALTM1:0>
(2) How to release the HALT mode
release sources are determined by the combinations between the states of the interrupt
mask register <IFF2:0> and the HALT modes. The details for releasing the halt status
are shown in Table 3.3.6.
•
•
HALT mode
These halt states can be released by resetting or by requesting an interrupt. The halt
Note: Usually, interrupts can release all halt status. However, the interrupts (
interrupt-enabled status being in force. When the interrupt request level set before
executing the HALT instruction exceeds the value of the interrupt mask register,
the interrupt due to that source is processed after releasing the HALT mode, and
then the CPU starts executing the next instruction that follows the HALT
instruction. When the interrupt request level set before executing the HALT
instruction is less than the value of the interrupt mask register, release of the
HALT mode is not executed. (In non-maskable interrupts, interrupt processing is
preformed after releasing the HALT mode regardless of the value of the mask
register.)
executed even if the interrupt request level set before executing the HALT
instruction is less than the value of the interrupt mask register. In this case
interrupt processing is not performed, and the CPU starts executing the next
instruction that follows the HALT instruction, but the interrupt request flag is
held at 1.
Release by requesting an interrupt
Release by resetting
This method of releasing operation from the HALT mode depends on the
INT0 interrupts are a special case in which release of the HALT mode is
Resetting releases all halt status settings.
When the STOP mode is released by reset, it is necessary to allow enough
INT0 to INT4, INTKEY, INTRTC) which can release the HALT mode may not be
able to do so if they are input during the period CPU is shifting to the HALT
mode (for about 3 clocks of f
are not applicable to this case). In this case, an interrupt request is kept on hold
internally.
If another interrupt is generated after it has shifted to HALT mode completely,
halt status can be released without difficulty. The priority of this interrupt is
compared with that of the interrupt kept on hold internally, and the interrupt with
higher priority is handled first followed by the other interrupt.
Table 3.3.5 I/O Operation during HALT Mode
Maintain the state when the HALT instruction was
executed.
93CS20-22
RUN
00
Operate
FPH
) with IDLE1 or STOP mode (RUN and IDLE2
IDLE2
11
Halt
IDLE1
10
Stop
See Table 3.3.8
TMP93CS20
STOP
2004-02-10
01
NMI
,