TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 250

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TMP93xy20FG

Manufacturer Part Number
TMP93xy20FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP93xy20FG

Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M/P
Rom Combinations
64
Ram Combinations
2
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
-
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
4
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
-
Dual Clock
Y
Number Of I/o Ports
88
Power Supply Voltage(v)
4.5 to 5.5
Symbol Name
SBISR
SBICR3
SBIDBR
I2CAR
Serial bus
interface
status
register
Serial bus
interface
status
register 3
Serial bus
interface
data buffer
register
I
address
register
2
C bus
Serial bus interface control (2/2)
Address
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(I
mode)
RMW)
mode)
RMW)
RMW)
RMW)
2
(SIO
4CH
4DH
4EH
4EH
4FH
C bus
0: Slave
1: Master
Monitor
select
status
MST
DB7
SA6
7
0
0
0: Receiver
1: Transmitter
Monitor
select status
TRX
DB6
SA5
6
0
0
0: Bus free
1: Bus busy
Monitor bus
status
93CS20-248
DB5
SA4
BB
5
0
0
R (Receiving)/W (Transmission)
Set slave address
0: Requesting
1: Release
Monitor
INTS2
interrumt
service
request
status
DB4
SA3
PIN
4
1
0
Undefined
W
R
1: Detect
0: End
1: Transferring
Monitor
arbitration
lost detect
Monitor serial
transferring
status
SIOF
DB3
SA2
AL
3
0
0
0
R
1: Detect
0: End
1: Setting
Monitor
slave
address
match
detect
Monitor
shift
operation
AAS
SEF
DB2
SA1
2
0
0
0
1: Detect
Monitor
general
call detect
AD0
DB1
SA0
1
0
0
TMP93CS20
2004-02-10
0: 0
1: 1
0: −
1: Initializa-
0: Acknowl-
1: Not
Monitor
last
receive bit
Initialize
SBI
internally
Speify
address
recogntion
mode
SWRST
tion
edges
slave
address
acknowl-
edge slave
address
LRB
R/W
DB0
ALS
0
0
0
0

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