TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 27

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

(Rising edge)
AD0 to AD15
INT0 (Level)
A0 to A23
Figure 3.3.7 Timing Chart of Halt State Release by Interrupts in IDLE1 Mode
INT0
CLK
ALE
NMI
WR
RD
X1
3.
IDLE1 mode
operates. The system clock in the MCU stops, and the CLK pin is fixed at the level
“H” in the output enabled state. (CKOCR<CLKEN> = 1)
system clock, however the halt release (Restart of operation) is performed
synchronously with it.
and internal interrupts (INTRTC). (See Table 3.3.6 “Halt Release Sources and
Halt Release Operations”.)
prescaler before a HALT instruction is executed, to reduce the power
consumption.
the IDLE1 mode.
In the IDLE1 mode, the internal oscillator and the timer for realtime clock
In the halt state, an interrupt request is sampled unsyncronously with the
IDLE1 mode is released by external interrupts (NMI, INT0 to INT4, INTKEY)
When the IDLE mode is used, set (TRUN<PRRUN> to 0) to stop the 9-bit
Figure 3.3.7 illustrates the timing for releasing the halt state by interrupts in
Address
Data
93CS20-25
IDLE1 mode
Address
Data
TMP93CS20
2004-02-10