TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 59

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TMP93xy20FG

Manufacturer Part Number
TMP93xy20FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP93xy20FG

Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M/P
Rom Combinations
64
Ram Combinations
2
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
-
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
4
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
-
Dual Clock
Y
Number Of I/o Ports
88
Power Supply Voltage(v)
4.5 to 5.5
P2
(0006H)
P2CR
(0008H)
P2FC
(0009H)
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Note 1: Read-modify-write is prohibited for registers P2CR and P2FC.
Note 2: When port P2 is used in the input mode, P2 register controls the built-in pull-up resistor. Read-modify-write
is prohibited in the input mode or the I/O mode, as it may affect the states of the pull-up resistor.
P27C
P27F
P27
7
7
7
0
0
P26C
P26F
P26
6
6
6
0
0
Figure 3.5.5 Registers for Port 2
Port 2 Function Register
Port 2 Control Register
Input mode (Output latch register is set to 1.)
P25C
P25F
P25
5
5
5
0
0
Port 2 Register
93CS20-57
<<See table below>>
<<See table below>>
P24C
P24F
Note:
P24
4
4
0
4
0
P2CR<P2XC>
R/W
W
W
<P2XF> is bit X in register P2FC; <P2XC> is bit X in
register P2CR. To set as an address bus A23 to A16, set
P2FC after setting P2CR.
P2FC<P2XF>
P23C
P23F
P23
0
1
3
3
0
3
0
P22C
P22F
P22
2
2
0
2
0
Output port
Input port
0
Port 2 function setting
P21C
P21F
P21
1
1
1
0
0
Address data bus
(A23 to A16)
Address bus
(A7 to A0)
P20C
P20F
P20
TMP93CS20
0
0
0
1
0
0
2004-02-10

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