TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 129

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

TAMOD
(0048H)
Bit symbol
Read/Write
After reset
Function
Figure 3.8.17 Registers for 16-Bit Timer/Event Counter (3/4)
7
6
Timer A Mode Control Register
0: Software
1: Don’t care
Control of
software
capture
CAPAIN
capture
W
5
1
93CS20-127
Capture timing
00: Disable
01: TIA↑
10: TIA↑
11: TFF1↑ TFF1↓
CAPABM1 CAPABM0
INTA occurs at rising
edge.
INTA occurs at rising
edge.
INTA occurs at falling
edge.
INTA occurs at rising
edge.
4
0
Timer A input clock
Clearing the up counter UCA
Capture timing of timer A
Software capture
TIB↑
TIA↓
00
01
10
11
00
01
10
11
0
1
0
1
3
0
Capture disable
CAPA at TIA rise
CAPB at TIB rise
CAPA at TIA rise
CAPB at TIA fall
CAPA at TFF1 rise
CAPB at TFF1 fall
External clock (TIA)
φT1
φT4
φT16
Clear disable
Clear by match with TREGB
The up counter A value is loaded to CAPA
Don’t care
Capture control
Control of
timer A
0: Clear
1: Clear
disable
enable
CLE
R/W
2
0
Timer A source clock
00: TIA
01: φT1
10: φT4
11: φT16
Interrupt occurs at
the rising edge of
TIA (INTA) input.
Interrupt occurs at
the faling edge of
TIA (INTA) input.
Interrupt occurs at
the rising edge of
TIA (INTA) input.
TACLK1
1
0
INTA control
TMP93CS20
TACLK0
2004-02-10
0
0