TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 193

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

<SIOS>
<SIOF>
<SEF>
SCK pin (Output)
SO pin
SI pin
INTS2
interrupt request
SBIDBR
c.
Figure 3.10.26 Transmit/Receive Mode (Example: Internal clock)
8-bit transmit/receive mode
After the data is written, set SBICR1<SIOS> to 1 to start transmitting/receiving.
When transmitting, the data is output from the SO pin on the leading edges in
synchronous with the serial clock, starting from the least significant bit (LSB).
When receiving, the data is input to the SI pin on the trailing edges of the serial
clock. The 8-bit data is transferred from the shift register to the SBIDBR, and the
INTS2 interrupt request occurs. The interrupt service program reads the received
data from the data buffer register and writes data to be transmitted. The SBIDBR
is used for both transmitting and receiving. Transmitted data should always be
written after received data is read.
received data is read and next data is written.
the external clock, received data is read and transmitted data is written before
new shift operation is executed. The maximum transfer speed when the external
clock is used is determined by the delay time between the time when an interrupt
request is generated and the time when received data is read and transmitted
data is written.
holds final bit of last data until falling edge of the SCK.
interrupt service program or setting SBICR1<SIOINH> to 1. When <SIOS> is
cleared, received data is transferred to the SBIDBR in complete blocks. The
transmit/receive mode ends when the transfer is complete. In order to confirm if
data is surely transmitted/received by the program, set SBISR<SIOF> to be
sensed. <SIOF> becomes 0 after transmitting/receiving is complete. When
<SIOINH> is set, transmitting/receiving data stops, <SIOF> turns 0.
Note: When the transfer mode is switched, the SBIDBR contents are lost. In case
Set a control register to a transmit/receive mode and write data to the SBIDBR.
When the internal clock is used, automatic wait function is initiated until
When the external clock is used, since the shift operation is synchronized with
When the transmit is started, after SBISR<SIOF> 1 output from the SO pin
Transmitting/receiving data is ended by clearing <SIOS> to 0 by the INTS2
that the mode needs to be switched, transmitting/receiving data is concluded
by clearing <SIOS> to 0, read the last data, and then switch the transfer mode.
Write
transmitted
data (a)
a
*
a 0
c 0
a 1
c 1
a 2
93CS20-191
c 2
a 3
c 3
a 4
c 4
Read received
a 5
c 5
a 6
c 6
data (c)
a 7
c 7
c
Write transmitted
data (b)
b
b 0
d 0
b 1
d 1
b 2
d 2
Clear <SIOS>
b 3
d 3
b 4
d 4
b 5
d 5
b 6
d 6
TMP93CS20
2004-02-10
Read received
data (d)
b 7
d 7
d