TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 160

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

SIOCLK
TXDCLK
(6) Receiving buffer
(7) Transmission counter
(8) Transmission controller
bits or 8 bits of data are stored in receiving buffer 1, the stored data is transferred to
receiving buffer 2 (SC0BUF) generating an interrupt INTRX0. The CPU reads only
receiving buffer 2 (SC0BUF). Even before the CPU reads receiving buffer 2 (SC0BUF),
the received data can be stored in receiving buffer 1. However, unless receiving buffer 2
(SC0BUF) is read before all bits of the next data are received by receiving buffer 1, an
overrun error occurs. If an overrun error occurs, the contents of receiving buffer 1 will
be lost, although the contents of the receiving buffer 2 and SC0CR<RB8> are still
preserved.
UART mode are stored in SC0CR<RB8>.
setting SC0MOD<WU> to 1, and interrupt INTRX0 occurs only when SC0CR<RB8> is
set to 1.
like a receiving counter, counts by the SIOCLK clock which generates TXDCLK every
16 clock pulses.
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transmission buffer is output bit by bit to TXD0 pin at the rising edge of the shift clock
which is output from the SCLK0 pin.
transmission buffer is output bit by bit to the TXD0 pin at the rising edge or falling
edge of the SCLK0 input according to the setting of the SC0CR<SCLKS> register.
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transmission starts at the rising edge of the next TXDCLK, generating a transmission
shift clock TXDSFT.
To prevent an overrun error, the receiving buffer has a double buffer structure.
Received data is stored bit by bit in receiving buffer 1 (Shift register type). When 7
The parity bit added in 8-bit UART mode and the most significant bit (MSB) in 9-bit
When in 9-bit UART mode, the wake-up function of the slave controller is enabled by
The transmission counter is a 4-bit binary counter which is used in UART mode and,
In SCLK output mode with the setting of SC0CR<IOC> = 0, the data in the
In SCLK input mode with the setting of SC0CR<IOC> = 1, the data in the
When transmission data is written to the transmission buffer sent from the CPU,
I/O interface mode
UART mode
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Figure 3.9.17 Generation of Transmission Clock
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93CS20-158
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TMP93CS20
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2004-02-10
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