TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 151

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

P6FC
(0016H)
P6ODE
(0058H)
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Prohibit read-modify-write.
Figure 3.9.9 Serial Transmission/Receiving Buffer Registers (Channel 1, SC1BUF)
Note: P6ODE<Bit7:4> and <Bit0> are read as 1.
SC1BUF
(0054H)
Note:
0: Port
1: TO1
RB7
TB7
P67F
7
7
Figure 3.9.11 Port 6 Open-drain Enable Register (P6ODE)
W
7
7
0
Prohibit read-modify-write for SC1BUF.
RB6
TB6
Figure 3.9.10 Port 6 Function Register (P6FC)
6
6
0: Port
1: INT7
I7IE
W
6
6
0
RB5
TB5
Setting P63 as open-drain output
5
5
0
1
0: Port
1: SCLK0
CMOS output
Open-drain output
TB4
RB4
4
4
P65F
W
5
5
0
93CS20-149
RB3
TB3
3
3
4
4
TB2
RB2
2
2
0: CMOS
1: Open drain
P63
0: Port
1: TXD0
RB1
TB1
ODE63
1
1
P63F
W
3
0
3
0
RB0
TB0
0
0
0: CMOS
1: Open drain
P62
0: Port
1: SCL/SI
Setting P63 as TXD0 output
Setting P65 as SCLK0 output
ODE62
P62F
R/W
(Transmission)
(Receiving)
0
1
0
1
W
Setting P61 as open-drain output
Setting P62 as open-drain output
2
0
2
0
0
1
0
1
Port output
TXD0 output (Channel 0)
Port output
SCLK0 output (Channel 0)
CMOS output
Open-drain output
CMOS output
Open-drain output
0: CMOS
1: Open drain
P61
0: Port
1: SDA/SO
ODE61
P61F
W
1
1
0
0
TMP93CS20
2004-02-10
0: Port
1: SCK
P60F
W
0
0
0