TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 46

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

INTE0AD
Symbol Address
INTE7S2
INTET10
INTET32
INTEBA
INTES0
INTES1
INTE21
INTE43
INTE98
lxxM2
lxxC
0070H
0071H
0072H
0073H
0074H
0075H
0076H
0077H
0078H
0079H
Note 1: Read-modify-write is prohibited.
Note 2: This note is about clearing interrupt request flags. The interrupt request flags of INTRX0 and INTRX1 are
0
0
0
0
1
1
1
1
0
1
(1) Interrupt priority setting register
Indicates no interrupt request.
Indicates interrupt request.
lxxM1
not cleared by writing 0 to IxxC because they are level-sense interrupts.
These interrupt request flags are cleared by clearing, resetting, or reading of the converted result or the
receive buffer.
ITX0C
ITX1C
IADC
IT1C
IT3C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IBC
I2C
I4C
I9C
I7C
0
0
1
1
0
0
1
1
7
0
0
0
0
0
0
0
0
0
0
Function (Read)
Figure 3.4.5 Interrupt Priority Setting Register (1)
lxxM0
ITX0M2
ITX1M2
IADM2
IT1M2
IT3M2
IBM2
I2M2
I4M2
I9M2
I7M2
INTT1 (TREG1)
INTT3 (TREG3)
0
1
0
1
0
1
0
1
6
0
0
0
0
0
0
0
0
0
0
INTTX0
INTTX1
INTAD
INTB
INT2
INT4
INT9
INT7
Prohibits interrupt request.
Sets interrupt request level to 1.
Sets interrupt request level to 2.
Sets interrupt request level to 3.
Sets interrupt request level to 4.
Sets interrupt request level to 5.
Sets interrupt request level to 6.
Prohibits interrupt request.
ITX0M1
ITX1M1
IADM1
IT1M1
IT3M1
I2M1
I4M1
I9M1
IBM1
I7M1
W
W
W
W
W
W
W
W
W
W
5
0
0
0
0
0
0
0
0
0
0
Clears interrupt request flag.
Don’t care
Function (Write)
93CS20-44
ITX0M0
ITX1M0
IADM0
IT1M0
IT3M0
I2M0
I4M0
I9M0
IBM0
I7M0
Function (Write)
4
0
0
0
0
0
0
0
0
0
0
IRX0C
IRX1C
IT0C
IT2C
IS2C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IAC
I0C
I1C
I3C
I8C
3
0
0
0
0
0
0
0
0
0
0
IRX0M2
IRX1M2
IS2M2
IT0M2
IT2M2
IAM2
I0M2
I1M2
I3M2
I8M2
INTT0 (TREG0)
INTT2 (TREG2)
2
0
0
0
0
0
0
0
0
0
0
INTRX0
INTRX1
INTS2
INTA
INT0
INT1
INT3
INT8
IRX0M1
IRX1M1
IS2M1
IT0M1
IT2M1
I0M1
I1M1
I3M1
I8M1
IAM1
W
W
W
W
W
W
W
W
W
W
1
0
0
0
0
0
0
0
0
0
0
IRX0M0
IRX1M0
IS2M0
IT0M0
IT2M0
I0M0
I1M0
I3M0
I8M0
IAM0
0
0
0
0
0
0
0
0
0
0
0
TMP93CS20
2004-02-10
←
←
←
←
Interrupt source
Bit symbol
Read/Write
After reset