TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 176

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

SBICR3
(004FH)
SBIDBR
(004CH)
I2CAR
(004DH)
Prohibit
read-
modify-
write
Prohibit
read-
modify-
write
Note 1: When writing the send data, start from the MSB (Bit7). Redeiving data is placed from LSB (Bit0).
Note 2: SBIDBR can’t be read the written data. Therefore read-modify-write instruction (e.g., “BIT” instruction) is
Note 3: Written data in SBIDBR is cleared by INTS2 signal.
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
Read/Write
Function
prohibitted.
DB7
SA6
7
7
7
0
Figure 3.10.6 Registers for I
Serial Bus Interface Data Buffer Register
Serial Bus Interface Control Register 3
DB6
SA5
6
6
6
0
I
2
C Bus Address Register
DB5
SA4
93CS20-174
5
5
5
0
Slave address selection.
R (Receive)/W (Send)
DB4
SA3
4
4
4
0
2
Undefined
C Bus Mode (4/4)
W
DB3
SA2
3
3
3
0
Address recognition mode specification
Software reset
0
1
0
1
Don’t care
Initialize SBI (after initializing SBI,
SWRST is automatically cleared to 0).
Slave address recognition
Non slave address recognition
DB2
SA1
2
2
2
0
DB1
SA0
1
1
1
0
TMP93CS20
Software
reset
0: Don’t
1: Initialize
Address
recognition
mode
specification
2004-02-10
SWRTS
care
SBI
R/W
DB0
ALS
0
0
0
0
0