TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 246

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

TREG8L
TREG8H
TREG9L
TREG9H
CAP8L
CAP8H
CAP9L
CAP9H
T8MOD
T8FFCR
Symbol
16-bit
timer
register 8
low
16-bit
timer
register 8
high
16-bit
timer
register 9
low
16 -bit
timer
register 9
high
Capture
register 8
low
Capture
register 8
high
Capture
register 9
low
Capture
register 9
high
16-bit
timer 8
source
CLK and
mode
16-bit
timer 8
flip-flop
control
Timer control (4/5)
Name
Address
(Prohibit
(Prohibit
(Prohibit
(Prohibit
RMW)
RMW)
RMW)
RMW)
30H
31H
32H
33H
30H
31H
32H
33H
38H
39H
7
6
93CS20-244
0: Soft-
1: Don’t
Inverted
when the
UC value
is latched
to CAP9
CAP8IN
CAP9T8
capture
care
W
5
1
0
Capture timing
00: Disable
01: TI8 ↑
10: TI8 ↑
11: TFF1 ↑ TFF1 ↓
Inverted
when the
UC value
is latched
to CAP8
CAP89M1
CAP8T8
TFF8 invert trigger
0: Trigger disable
1: Trigger enable
4
0
0
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
R/W
W
W
W
W
R
R
R
R
−
−
−
−
−
−
−
−
TI9 ↑
TI8 ↓
Inverted
when the
UC value
matches
TREG9
CAP89M0
EQ9T8
3
0
0
1: UC8
Inverted
when the
UC value
matches
TREG8
EQ8T8
clear
enable
CLE
R/W
2
0
0
Source clock
00: TI8 input
01: φT1
10: φT4
11: φT16
00: Invert TFF8
01: Set TFF8
10: Clear TFF8
11: Don’t care
T8CLK1
TFF8C1
1
0
1
TMP93CS20
2004-02-10
W
T8CLK0
TFF8C0
0
0
1