TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 132

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

(5) Capture input control
(6) Comparator
(7) Timer flip-flop (TFF8)
and CAP9. The latch timing of the capture register is controlled by register
T8MOD<CAP89M1:0>. There are four possible settings:
•
•
•
•
Whenever 0 is written in T8MOD<CAP8IN>, the current value of the up counter will
be loaded to capture register CAP8. It is necessary to keep the prescaler in RUN mode
(TRUN<PRRUN> has to be 1).
values set in TREG8 and TREG9 to detect matches. When a match is detected, these
comparators generate interrupts INTTR8 or INTTR9 respectively. The up counter UC8
is cleared only when UC8 matches TREG9. The clearing of up counter UC8 can be
disabled by setting T8MOD<CLE> = 0.
signals to the capture registers. Disable or enable of inversion can be set for each
element by T8FFCR<CAP9T8, CAP8T8, EQ9T8, and EQ8T8>. TFF8 will be inverted
when 00 is written in T8FFCR<TFF8C1:0>. Also it is set to 1 when 01 is written, and
cleared when 10 is written. The value of TFF8 can be output to the timer output pin
TO8 (which is also used as P72). To output to the timer output pin, TFF8 must be set by
the Port 7 function register, P7FC beforehand (See “Registers for Port 7”).
This circuit controls the timing of latching the value of up counter UC8 into CAP8
Besides, the value of the up counter can be loaded to capture registers by software.
There are 16-bit comparators which compare the up counter UC8 value with the
This flip-flop is inverted by the match detect signal from the comparators or the latch
When T8MOD<CAP89M1:0> = 00
When T8MOD<CAP89M1:0> = 01
When T8MOD<CAP89M1:0> = 10
When T8MOD<CAP89M1:0> = 11
P70 or INT8) input, while data are loaded to CAP9 at the rising edge of the TI9 pin
(also used as P71 or INT9) input.
the falling edge. Only in this setting, interrupt INT8 occurs at the falling edge.
at the falling edge.
Capture function is disabled. Disable is the default on resetting.
Data are loaded to CAP8 at the rising edge of the TI8 pin (which is also used as
Data are loaded to CAP8 at the rising edge of the TI8 pin input, and to CAP9 at
Data are loaded to CAP8 at the rising edge of timer flip-flop TFF1, and to CAP9
93CS20-130
TMP93CS20
2004-02-10