TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 104

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

TREG2-WR
TRDC<TR2DE>
Match with TREG2
and up counter 2
Match with TREG3
TREG2
(Value to be compared)
Register buffer
will be shifted in TREG2 each time TREG3 matches UC2.
varied).
Example:
TI2
φT1
φT4
φT16
Selector
When the double buffer of TREG2 is enabled in this mode, the value of the register buffer
Use of the double buffer makes the handling of low duty waves easy (when duty is
T32MOD<T2CLK1:0>
Generating 1/4 duty 62.5 kHz pulse (at fc = 20 MHz)
Shift trigger
Selector
Figure 3.7.14 Block Diagram of 8-Bit PPG Output Mode
*
Register buffer
Comparator
Figure 3.7.15 Operation of Register Buffer
Clock condition
TREG2
16 µs
Internal data bus
Signifies that data is transferred to TREG2.
(Up counter = Q
up counter
(UC2)
8-bit
93CS20-102
Q
1
Comparator
TREG3
1
)
Q
2
System clock:
Clock gear:
Prescaler clock: f
TRUN<T2RUN>
(Up counter = Q
Shift from register buffer
High frequency (fc)
1 (fc)
FPH
TFF3
TO3
2
)
Inversion
Q
TREG2 (Register buffer)
write
2
TFFCR
<TFF3C1, TFF3C0,
TFF3IE>
Q
INTT2
INTT3
3
TMP93CS20
2004-02-10