TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 166

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

Figure 3.9.24 Receiving Operation in I/O Interface Mode (SCLK0 output mode)
Figure 3.9.25 Receiving Operation in I/O Interface Mode (SCLK0 input mode)
b.
IRX0C
SCLK0
RXD0
Timing to shift data in
the receiving buffer 2
SCLK0 input
(SCLKS = 0:
Rising edge mode)
SCLK0 input
(SCLKS = 1:
Falling edge mode)
RXD1
Timing to shift data in
the receiving buffer 2
Note: For data receiving, the system must be placed in the receive enable state
Receiving
the data is shifted to receiving buffer 1. This starts when the receive interrupt flag
INTES0<IRX0C> is cleared by reading the received data. When 8-bit data are
received, the data will be transferred to receiving buffer 2 (SC0BUF according to
the timing shown below) and INTES0<IRX0C> will be set again to generate
INTRX0 interrupt.
input becomes active after the receive interrupt flag INTES0<IRX0C> is cleared
by reading the received data. When 8-bit data is received, the data will be shifted
to receiving buffer 2 (SC0BUF according to the timing shown below) and
INTES0<IRX0C> will be set again to generate INTRX0 interrupt.
In SCLK output mode, the synchronous clock is outputted from SCLK0 pin and
In SCLK input mode, the data is shifted to receiving buffer 1 when the SCLK
(SC0MOD<RXE> = 1)
(Channel 0)
(Channel 0)
Bit0
93CS20-164
Bit0
Bit1
Bit2
Bit1
Generate INTRX0
Bit6
Bit2
Bit7
Generate INTRX0
Bit6
TMP93CS20
Bit7
2004-02-10