TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 13

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

3.3
Dual Clock, Standby Function
controller, internal clock pin output function and standby controller.
X1 and X2 pins), or (b) dual clock mode (Using the X1, X2, XT1, and XT2 pins).
corresponding block diagram, Figure 3.3.3 displays functions of the I/O registers and Table
3.3.1 lists correspondences between alternative states of the system clock and those of the CPU,
oscillator and internal I/O components.
from the XT1 and XT2 pins is called fs. The clock frequency selected by SYSCR1<SYSCK> is
called the system clock f
one cycle of f
Dual clock, standby control circuits are comprised of a system clock controller, prescaler clock
The oscillator operating modes are classified as either (a) single clock mode (Using only the
Figure 3.3.1 shows state diagrams for the two clock modes. Figure 3.3.2 shows the
The clock frequency input from the X1 and X2 pins is called fc, and the clock frequency input
(Operates only oscillator)
(Stops CPU and AD)
(Operates only oscillator)
(Operates only oscillator)
(Stops CPU and AD)
(Stops CPU and AD)
(Stops only CPU)
(Stops only CPU)
(Stops only CPU)
IDLE2 mode
IDLE1 mode
RUN mode
IDLE2 mode
IDLE1 mode
IDLE2 mode
IDLE1 mode
RUN mode
RUN mode
SYS
is defined as one state.
Instruction
Interrupt
Instruction
Interrupt
Interrupt
Instruction
Interrupt
Instruction
Instruction
Interrupt
Instruction
Interrupt
Instruction
Instruction
FPH
Interrupt
Interrupt
Interrupt
Instruction
. The divided clock of f
Figure 3.3.1 State Diagrams
(a) Single clock mode state diagram
(b) Dual clock mode state diagram
93CS20-11
(fc/gear value/2)
NORMAL mode
(fc/gear value/2)
NORMAL mode
SLOW mode
Instruction
Reset
Reset
(fs/2)
Release reset
Release reset
FPH
is defined as the system clock f
Instruction
Interrupt
Instruction
Instruction
Interrupt
(Stops all circuits)
STOP mode
(Stops all circuits)
STOP mode
TMP93CS20
2004-02-10
SYS
, and