TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 247

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

TREGAL
TREGAH
TREGBL
TREGBH
CAPAL
CAPAH
CAPBL
CAPBH
TAMOD
TAFFCR
Symbol
16-bit timer
register A
low
16-bit timer
register A
high
16-bit timer
Register B
low
16-bit timer
register B
high
Capture
register A
low
Capture
register A
high
Capture
register B
low
Capture
register B
high
16-bit
timer A
source
CLK and
mode
16-bit
timer A
flip-flop
control
Timer control (5/5)
Name
Address
(Prohibit
(Prohibit
(Prohibit
(Prohibit
RMW)
RMW)
RMW)
RMW)
40H
41H
42H
43H
40H
41H
42H
43H
48H
49H
7
6
93CS20-245
0: Soft-
1: Don’t
CAPBTA
Inverted
when the
UC value
is latched
to CAPB
CAPAIN
capture
care
W
5
1
0
CAPABM1
Capture timing
00: Disable
01: TIA ↑
10: TIA ↑
11: TFF1 ↑ TFF1 ↓
CAPATA
Inverted
when the
UC value
is latched
to CAPA
TFFA invert trigger
0: Trigger disable
1: Trigger enable
4
0
0
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
R/W
W
W
W
W
R
R
R
R
−
−
−
−
−
−
−
−
TIB ↑
TIA ↓
CAPABM0
EQBTA
Inverted
when the
UC value
matches
TREGB
3
0
0
1: UC5
EQATA
Inverted
when the
UC value
matches
TREGA
clear
enable
CLE
R/W
2
0
0
Source clock
00: TIA input
01: φT1
10: φT4
11: φT16
TFFAC1
00: Invert TFFA
01: Set TFFA
10: Clear TFFA
11: Don’t care
TACLK1
1
0
1
TMP93CS20
2004-02-10
W
TFFAC0
TACLK0
0
0
1