TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 60

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

3.5.4
Port 3 (P30 to P37)
using control register P3CR and function register P3FC. Resetting sets all bits of output
latch P3 to 1, and control register P3CR (Bits 0 and 1 are unused) and function register
P3FC to 0. Resetting also outputs 1 from P30 and P31, sets P32 to P37 to input mode, and
connects a pull-up resistor.
for the CPU’s control/status signal, an input for INT0 to INT4 and an analog conversion
external trigger input
ROM is used, clearing the output latch register <P30> to 0 outputs the
the pseudo-static RAM) from the P30 pin even when the internal address area is accessed.
the external address area is accessed.
(1) P30 (
Port 3 is an 8-bit general-purpose I/O port.
I/O can be set on a bit basis, but note that P30 and P31 are used for output only. I/O is set
In addition to functioning as a general-purpose I/O port, port 3 also functions as an I/O
When the P30 pin is defined as
If the output latch register <P30> remains 1, the
RD
), P31 (
Function control
P3 read
(on bit basis)
Output latch
P3FC write
P3 write
WR
Reset
Figure 3.5.6 Port 3 (P30 and P31)
S
ADTRG
)
.
93CS20-58
RD
RD
A
B
,
WR
signal output mode (<P30F> = 1), in the external
S
Output buffter
RD
strobe signal is output only when
P30 (
P31 (
RD
RD
WR
)
strobe (Used for
)
TMP93CS20
2004-02-10