TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 182

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

SCL pin
SDA pin
<PIN>
INTS2
interrupt request
3.10.5
Data Transfer in I
(1) Device initialization
(2) Start condition and slave address generation
addressing format).
0 and 1 in the SBICR2. The slave receiver mode is set.
transmitted to the SBIDBR.
and the direction bit which are set to the SBIDBR are output on a bus by wiring 1 to
the SBICR2<MST, TRX, BB> and PIN. An INTS2 interrupt request occurs at the 9th
falling edge of the SCL clock cycle, and the <PIN> is cleared to 0. The SCL pin is pulled
down to the low-level while the <PIN> is 0. When an interrupt request occurs, the
<TRX> changes by the hardware according to the direction bit only when an
acknowledge signal is returned from the slave device.
Note 1: Do not write a slave address to be output to the SBIDBR while data are transferred.
Note 2: Do not start transferring due to another master from writing a slave address to be
Figure 3.10.12 Start Condition Generation and Slave Address Transfer
Note: The initialization of the serial bus interface circuit must be complete within the time
First, set SBICR1<ACK, SCK2:0>. Specify 0 to bits 7 to 5 and 3 in the SBICR1.
Set the slave address <SA6:0> and <ALS> to I2CAR (<ALS> = 0 when the
Subsequently, set 0 to <MST, TRX, BB>; 1 to <PIN>; 10 to <SBIM1:0>; and 0 to bits
Confirm a bus free status (when SIBSR<BB> = 0).
Set the SBICR1<ACK> to 1 and specify a slave address and a direction bit to be
When the SBISR<BB> is 0, the start condition are generated and the slave address
Start condition
from all devices which are connected to the bus have initialized to any device does
not generate a start condition. If not, there is a possibility that another device starts
transferring before an end of the initialization of the serial bus interface circuit. Data
can not be received correctly.
If data is written to the SBIDBR, data to been outputting may be destroyed.
output to the SBIDBR to writing a start condition generation command to the
SBICR2. The serial bus interface circuit malfunctions because it has not an
arbitration function.
A6
1
2
C Bus Mode
A5
2
A4
3
93CS20-180
Slave address + Direction bit
A3
4
A2
5
A1
6
A0
7
R/
8
W
9
TMP93CS20
2004-02-10
Acknowledge
signal from a
slave device