TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 248

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

SC0MOD
SC1MOD
Symbol Name
SC0BUF
BRADD0
SC1BUF
SC0CR
BR0CR
SC1CR
(7) Serial channel control (1/2)
Serial
channel
0 buffer
Serial
channel
0 control
Serial
channel
0 Mode
Baud
rate 0
control
Baud
rate
control
Serial
channel
1 buffer
Serial
channel
1 control
Serial
channel
1 mode
Address
(Prohibit
(Prohibit
RMW)
RMW)
50H
51H
52H
53H
68H
54H
55H
56H
Transmisson
data bit8
Transmisson
data bit8
Receiving
data bit8
Always
fixed to “0”.
Receiving
data bit8
Undefined
Undefined
Undefined
Undefined
RB7
RB8
R/W
RB7
RB8
TB7
TB8
TB7
TB8
－
7
R
R
0
1: CTS
Always
fixed to “0”.
Parity
0: Odd
1: Even
1: + (16 − K)
Parity
0: Odd
1: Even
BR0ADD
enable
/16 divisor
enable
CTSE0
EVEN
EVEN
RB6
RB6
TB6
TB6
6
0
0
0
0
−
0
R/W
R/W
1: Receive
1: Parity
1: Receive
1: Parity
93CS20-246
enable
BR0CK1
enable
enable
enable
RXE
RXE
RB5
RB5
TB5
TB5
PE
PE
5
0
0
0
0
0
R (Receiving) /W (Transmission)
00: φT0
01: φT2
10: φT8
11: φT32
R (Receiving)/W (Transmission)
Overrun
1: Wake-up
Overrun
1: Wakeup
BR0CK0
enable
enable
OERR
OERR
RB4
RB4
TB4
TB4
WU
WU
R (Cleared to “0” by reading)
R (Cleared to 0 by reading)
4
Undefined
Undefined
0
0
0
0
0
R/W
R/W
Parity
00: I/O Interface
01: UART 7 bits
10: UART 8 bits
11: UART 9 bits
Parity
00: Reserved
01: UART 7 bits
10: UART 8 bits
11: UART 9 bits
1: Error
1: Error
BR0S3
R/W
BR0K3
PERR
PERR
SM1
SM1
RB3
RB3
TB3
TB3
3
0
0
0
0
0
0
Set N + (16 − K)/16 divisor
Framing
Framing
Set frequency divisor
BR0S2
BR0K2
1 to F (0 prohibited)
FERR
FERR
SM0
SM0
RB2
TB2
RB2
TB2
2
0
0
0
0
0
0
0 to F
R/W
00: TO0 trigger
01: Baud rate generator
10: Internal clock φ1
11: External clock SCLK0
Always fixed to “0”.
00: TO0 trigger
01: Baud rate generator
10: Internal clock φ1
11: Don’t care
0: SCLK0
1: SCLK0
SCLKS
BR0S1
BR0K1
RB1
SC1
RB1
SC1
TB1
TB1
1
0
0
0
0
−
0
0
TMP93CS20
2004-02-10
R/W
R/W
1:
SCLK0
pin
BR0S0
BR0K0
Input
RB0
SC0
RB0
SC0
TB0
IOC
TB0
0
0
0
0
0
−
0
0