TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 87

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TMP93xy20FG

Manufacturer Part Number
TMP93xy20FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP93xy20FG

Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M/P
Rom Combinations
64
Ram Combinations
2
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
-
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
4
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
-
Dual Clock
Y
Number Of I/o Ports
88
Power Supply Voltage(v)
4.5 to 5.5
Figure 3.6.1 Example of External Memory Connection (ROM and RAM = 16 bits)
Example of Usage
TMP93CS20
SRAM
ROM
TMP93CS20. In this example, a 128-Kbyte ROM is connected using a 16-bit bus, and a
256 Kbyte RAM is connected using a 16-bit bus.
Upper address
insufficient capacity, it is possible to connect an external memory following the usage
examples for this purpose. In this example, the memory configuration is as follows.
AD8 to AD15
Figure 3.6.1 is an example in which an external memory is connected to the
AD0 to AD7
The TMP93CS20 has built-in ROM and RAM. When ROM and RAM have
Memory
A16 to A17
HWR
Internal
External
Internal
External
WR
ALE
RD
EA
64 Kbytes
128 Kbytes
2 Kbytes
256 Kbytes
Decoder
Latch × 16
Memory Size
D
LE
Q
ROMCS
RAMCS
93CS20-85
FF0000H to FFFFFFH
400000H to 41FFFFH
0000A0H to 00089FH
800000H to 83FFFFH
A16
A1 to A15
A16 to A17
A1 to A15
A16 to A17
A1 to A15
Address
A15
A0 to A14
A15 to A16
A0 to A14
R/
A15 to A16
A0 to A14
R/
OE
CS
OE
CS
OE
CS
W
W
ROM (64 Kbytes × 16)
RAM (128 Kbytes × 8)
RAM (128 Kbytes × 8)
Upper byte
Lower byte
Data Bus
16 bits
16 bits
16 bits
16 bits
I/O1 to I/O8
I/O1 to I/O8
D8 to D15
D0 to D7
TMP93CS20
2004-02-10

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