TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 192

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

<SIOS>
<SIOF>
<SEF>
SCK pin (Output)
SI pin
INTS2
interrupt request
SBIDBR
b.
8-bit receive mode
to the receive mode. Data is received from the SI pin to the shift register in
synchronous with the serial clock, starting from the least significant bit (LSB).
When the 8-bit data is received, the data is transferred from the shift register to
the SBIDBR. The INTS2 (Buffer full) interrupt request is generated to request to
read the received data. The data is then read from the SBIDBR by the interrupt
service program.
function will be initiated until the received data is read from the SBIDBR.
clock pulse provided externally, the received data should be read from the
SBIDBR before next serial clock input. If the received data is not read, further
data to be received is canceled. The maximum transfer speed when the external
clock is used is determined by the delay time between the time when an interrupt
request is generated and the time when received data is read.
service program or setting SBICR1<SIOINH> to 1. When <SIOS> is cleared,
received data is transferred to the SBIDBR in complete blocks. The received mode
ends when the transfer is complete. In order to confirm if data is surely received
by the program, set SBISR<SIOF> to be sensed. <SIOF> is cleared to 0 when
receiving is complete. After confirming that receiving has ended, the last data is
read. When <SIOINH> is set to 1, receiving data stops, <SIOF> turns 0. (The
received data becomes invalid, therefore no need to read it.)
Note: When the transfer mode is switched, the SBIDBR contents are lost. In case
Set the control register to a receive mode and SBICR1<SIOS> to 1 for switching
When the internal clock is used, the serial clock will stop and automatic wait
When the external clock is used, since shift operation is synchronized with the
Receiving data is ended by clearing <SIOS> to 0 with the buffer full interrupt
Figure 3.10.25 Receive Mode (Example: Internal clock)
that the mode needs to be switched, receiving data is concluded by clearing
<SIOS> to 0, read the last data, and then switch the mode.
a 0
a 1
a 2
93CS20-190
a 3
a 4
a 5
Read received data
a 6
a 7
a
b 0
b 1
b 2
Clear <SIOS>
b 3
b 4
b 5
Read received data
b 6
b 7
TMP93CS20
2004-02-10
b