TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 210

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

3.12.3
Operation
WDMOD<WDTP1:0>. The watchdog timer must be cleared to 0 by software before an
INTWD interrupt is generated. If the CPU malfunctions (Undergoes runaway) due to
causes such as noise, but does not execute the instruction used to clear the binary counter,
the binary counter overflows and an INTWD interrupt is generated. The CPU detects
malfunction (Runaway) from the INTWD interrupt and it is possible to return to normal
operation using a recovery program. By connecting the watchdog timer out pin to
peripheral devices resets, a CPU malfunction can also be acknowledged to other devices.
watchdog timer before entering the halt state to prevent a watchdog timer interrupt.
Example:
a.
WDCR
b.
WDMOD
c.
WDMOD
WDCR
d.
WDMOD
WDCR
Executes Halt command
e.
WDMOD
Executes Halt command
X: Don't care, −: No change
The watchdog timer generates interrupt INTWD after the detection time set in the
The watchdog timer restarts operation immediately after reset is released.
The watchdog timer does not operate in IDLE1 or STOP mode.
The watchdog timer is enabled in RUN or IDLE2 mode. In IDLE2 mode, disable the
Clear the binary counter.
Set the watchdog timer detecting time to 2
Disable the watchdog timer.
Set IDLE1 mode.
Set the STOP mode (warm-up time: 2
← 0 1 0 0 1 1 1 0
← 1 0 1 − − − X X
← 0 − − − − − X X
← 1 0 1 1 0 0 0 1
← 0 − − − 1 0 X X
← 1 0 1 1 0 0 0 1
← − − − 1 0 1 X X
93CS20-208
16
/f
SYS
17
/f
)
SYS
.
Write clear code (4EH).
Clear WDTE to 0.
Write disable code (B1H).
Disable WDT and set IDLE1 mode.
Set HALT mode.
Set the STOP mode.
Set HALT mode.
TMP93CS20
2004-02-10