TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 143

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

3.9.1
temporarily store transmitted or received data. This is done so that transmitting and receiving
operations can be done independently (Full duplex).
receiving, the channel becomes half duplex.
overrun error and it provides one data format of margin before the CPU reads the received data.
The receiving data register stores the previously received data while the buffer register receives
the next frame data.
software.) it is possible to halt data send until the CPU finishes reading receive data every time
a frame is received (Handshake function).
erroneous start bits due to noise. The channel starts receiving data only when the start bit is
detected to be normal at least twice in three samplings of the start bit.
transmission data, or when data is stored in the receiving data register and the CPU is
requested to read the data, INTTX (Transmit interrupt) or INTRX (Receive interrupt) interrupt
occurs. If an overrun error, parity error, or framing error occurs during receiving operation, flag
SC0CR<OERR, PERR, FERR> will be set.
by dividing the frequency of 4 clocks (φT0, φT2, φT8, and φT32) from the 9-bit prescaler shared
by the 8-bit/16-bit timers by the value 1, 2 + n/16 to 15 + n/16, 16 (n = 0 to 15).
(SCLK0) can set to any baud rate. (Serial channel 0)
receive data by using an external clock.
The serial channel has buffer registers for transmitting and receiving operations in order to
However, in I/O interface mode, the SCLK (Serial clock) pin is used for both transmitting and
The receiving data register is a double buffer structure to prevent the occurrence of an
By using
In the UART mode, a check function is added to not start the receiving operation by
When the transmission buffer becomes empty and requests the CPU to send the next
The serial channels 0, 1 include a special baud rate generator, which can set to any baud rate
Not only clocks from the internal baud rate generator but also the external input clock
In I/O interface mode, it is possible to input synchronous signals as well as to transmit or
Note: The number of the control register name is equaled to the channel number.
Control Registers
BRADD0. Transmitted and received data are stored in register SC0BUF.
The serial channels are controlled by 4 control registers SC0CR, SC0MOD, BR0CR, and
CTS
and
RTS
(There is no
93CS20-141
RTS
pin, so any single port must be controlled by
TMP93CS20
2004-02-10