TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 84

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

3.6.2
Bus Width/Wait Control Registers
registers WAITC0, WAITC1, and WAITC2.
(1) Data bus size select
(2) Wait control
(3) Address area specification
Table 3.6.1 shows control registers.
One block of the address areas is controlled by each of the 1-byte bus width/wait control
size. Setting this bit to 0 accesses the memory in 16-bit data bus mode; setting it to 1
accesses the memory in 8-bit data bus mode.
Table 3.6.1 shows the details of the bus operation.
number of waits. Setting these bits to 00 inserts a 2-state wait regardless of the
pin status. Setting them to 01 inserts a 1-state wait regardless of the
Setting them to 10 inserts a 1-state wait and samples the
is low, inserting the wait maintains the bus cycle until the pin goes high. Setting them
to 11 completes the bus cycle without a wait, regardless of the
target address area. Setting these bits to 00 enables settings as follows:
space 400000H to 7FFFFFH is accessed. Setting these bits to 10 enables when the
address space 800000H to BFFFFFH to be accessed. Setting these bits to 11 enables
when the address space C00000H to FFFFFFH to be accessed.
*
*
*
Bit4 (B0BUS, B1BUS, and B2BUS) of the control register is used to specify data bus
Changing data bus size depending on the access address is called dynamic bus sizing.
Control register bits 3 and 2 <B0W1:0, B1W1:0, and B2W1:0> are used to specify the
Resetting sets these bits to 00 (2-state wait mode).
Control register bits 1 and 0 <B0C1:0, B1C1:0, and B2C1:0> are used to specify the
Setting these bits to 01 enables settings for all WAITC’s blocks when the address
The WAITC0 setting is enabled when the address space 7F00H to 7FFFH is
accessed.
The WAITC1 setting is enabled when the address space 8A0H to 7FFFH is
accessed.
The WAITC2 setting is enabled when the address space 8000H to 3FFFFFH is
accessed,
93CS20-82
WAIT
WAIT
pin status. If the pin
pin status.
TMP93CS20
WAIT
2004-02-10
status.
WAIT