TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 107

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

Match with TREG2
2
TREG2
(Value to be compared)
Register buffer
n
− 1 overflow
Example:
TRUN
T32MOD
TREG2
TFFCR
P8CR
P8FC
TRUN
overflow is detected while the double buffer of TREG2 is enabled.
In this mode, the value of the register buffer will be shifted into TREG2 if a 2
Use of the double buffer makes easy the handling of small-duty waves.
To output the following PWM waves to the TO3 pin at fc = 20 MHz.
← − X − − − 0 − −
← 1 1 1 0 − − 0 1
← 0 1 0 0 1 0 0 0
← 1 0 1 X − − − −
← − − − − 1 − − −
← X X X X 1 X X −
← 1 X − − − 1 − −
X: Don’t care, −: No change
*
To realize a PWM cycle of 50.8 µs by utilizing φT1 = 0.4 µs (at fc = 20 MHz),
Consequently, n should be set to 7.
As the period of low level is 28.8 µs, for φT1 = 0.4 µs,
set the following value for TREG2.
MSB
7 6 5 4 3 2 1 0
Figure 3.7.18 Operation of Register Buffer
Clock condition
50.8 µs ÷ 0.4 µs = 127 = 2
28.8 µs ÷ 0.4 µs = 72 = 48H
28.8 µs
50.8 µs
Up counter = Q
93CS20-105
Q
LSB
1
1
n
− 1
Q
2
System clock:
Clock gear:
Prescaler clock: f
Stop timer 2 and clear it.
Set 8-bit PWM mode (cycle: 2
input clock.
Writes 48H.
Clear TFF3, enable the inversion and double buffer.
Set P83 as the TO3 pin.
Start timer 2 counting.
High frequency (fc)
1 (fc)
FPH
Shift into TREG2
Up counter = Q
7
− 1) and select φT1 as the
Q
TREG2 (Register buffer)
write
2
2
TMP93CS20
Q
3
2004-02-10
n
− 1