TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 23

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

WDMOD
(005CH)
3.3.4
Bit symbol
Read/Write
After reset
Function
Standby Controller
(1) HALT mode
IDLE1, or STOP mode depending on the contents of the HALT mode setting register
WDMOD<HALTM1:0>. Figure 3.3.5 shows the alternative states of the watchdog
timer mode registers.
1.
2.
3.
4.
When the HALT instruction is executed, the operating mode changes to RUN, IDLE2,
The features of the RUN, IDLE2, IDLE1, and STOP modes are as follows.
The operations in the halt state are described in Table 3.3.5.
0: Disable
1: Enable
Watchdog
timer
control
WDTE
RUN:
IDLE1: Only the built-in oscillator and the clock timer operate, while all other
STOP: All internal circuits including the built-in oscillator stop. This greatly
IDLE2: The built-in oscillator and the specified I/O operates.
7
1
Figure 3.3.5 Watchdog Timer Mode Register
Watchdog timer detect
time selection
00: 2
01: 2
10: 2
11: 2
Only the CPU halts; power consumption remains unchanged.
The power consumption is reduced to 1/2 than that during NORMAL
operation.
built-in circuits stop. Consumption is reduced to 1/5 or less than that
during NORMAL operation.
reduces power consumption.
WDTP1
6
0
15
17
19
21
/f
/f
/f
/f
Watchdog Timer Mode Register
SYS
SYS
SYS
SYS
WDTP0
5
0
93CS20-21
0: 2
1: 2
Warm-up
timer
WARM
frequency
selection
frequency
selection
14
16
/clock
/clock
4
0
R/W
HALT mode selection
00: RUN mode
01: STOP mode
10: IDLE1 mode
11: IDLE2 mode
HALTM1
Pin state control in STOP mode
HALT mode setting
Warm-up time selection at returning from the
STOP mode (See Table 3.3.7)
00
01
10
11
3
0
0
1
0
1
I/O off
Retains the state before halt
RUN mode (only CPU stops)
STOP mode (All circuits stop)
IDLE1 mode (only clock timer operating)
IDLE2 mode (Partial I/O operation)
2/
2/
14
16
HALTM0
select clock frequency
select clock frequency
2
0
1: Executes
Runaway
detection
internal
reset control
RESCR
internal
reset by
runaway
detection
1
0
TMP93CS20
2004-02-10
1: Drive
STOP
mode pin
control
pins in
STOP
mode
DRVE
0
0