TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 150

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

BR1CR
(0057H)
BRADD1
(006CH)
BRADD1
<BR1K3:0>
1111 (K = 15)
0001 (K = 1)
+ (16 − K)/16 division enable
0
1
Bit symbol
Read/Write
After reset
Function
Bit Symbol
Read/Write
After reset
Function
0000
to
Note 1: Set TRUN<PRRUN> to 1 when the baud rate generator is used.
Note 2: Set BR1CR<BR1ADD> to 1 after setting K (K = 1 to 15) to BRADD1<BR1K3:0> when + (16 − K)/16 division
Note 3: Channel 1 is used only in UART mode, I/O interface mode is not possible to use.
Note 4: BRADD1<Bit7:4> is always read as 1.
Note 5: Don't read from or write to BR1CR and BRADD1 register during sending or receiving.
Disable
Enable
BR1CR
<BR1S3:0>
Figure 3.9.8 Baud Rate Generator Control (Channel 1, BR1CR, BRADD1)
function is used. However, don't use + (16 − K)/16 division function when <BR1K3:0>set to 0000 or 0001.
Always
fixed to 0
Sets baud rate generator frequency divisor
7
7
−
0
0000 (N = 16)
0001 (N = 1)
+ (16 − K)/16
division
0: Disable
1: Enable
Disable
Disable
BR1ADD
or
BR1CR<BR1ADD> = 1
6
6
0
Selecting the input clock of baud rate generator
00
01
10
11
00: φT0
01: φT2
10: φT8
11: φT32
BR1CK1
Internal clock φT0
Internal clock φT2
Internal clock φT8
Internal clock φT32
5
5
0
93CS20-148
N + (16 − K)/16
1111 (N = 15)
0010 (N = 2)
Divided by
Disable
to
BR1CK0
4
4
0
R/W
BR1CR<BR1ADD> = 0
BR1S3
BR1K3
3
0
3
0
1111 (N = 15)
0000 (N = 16)
Divided by N
0001 (N = 1)
Setting of the divided frequency
to
(divided by N
Sets frequency divisor “K”
BR1S2
BR1K2
2
0
2
0
R/W
+
(16 − K)/16)
BR1S1
BR1K1
1
1
0
0
TMP93CS20
2004-02-10
BR1S0
BR1K0
0
0
0
0