TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 35

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

(1) Maskable interrupt
(3) Interrupt nesting
(5) Timing of interrupt acceptance
During execution of the main program, the CPU accepts an
interrupt request. The CPU then increments IFF so that no
new interrupts of priority level 1 will be accepted during
processing of the interrupt routine.
During processing an interrupt of priority level 3, the IFF is set to
4. When an interrupt with a level higher than 4 is generated, the
CPU accepts the interrupt with the higher priority level, causing
interrupt processing to nest.
If an interrupt with a priority level higher than the interrupt
currently being processed is generated, the CPU accepts the
interrupt with the higher level. The program counter which
returns at [5] is the state address of the INTT0 interrupt routine.
(Level 1)
(Level 3)
(Level 3)
(Main)
INTT0
(Main)
INTT0
(Main)
INTT0
EI 1
EI 3
EI 3
[1]
[5]
[1]
[9]
[1]
[8]
(INTT0 interrupt routine) (INTT1 interrupt routine)
(INTT0 interrupt routine) (INTT1 interrupt routine)
(Level 4)
INTT1
IFF ← 2
IFF ← 1
IFF ← 4
IFF ← 3
(INTT0 interrupt routine)
[2]
[2]
[4]
[2]
[8]
[7]
(Level 4)
INTT1
RETI
RETI
RETI
XXX
[3]
[3]
[7]
[6]
[3]
[5]
IFF ← 5
IFF ← 4
93CS20-33
RETI
[4]
[6]
[4]
RETI
[5]
(2) Non-maskable interrupt
The DI instruction is executed in the main program, so
that only interrupts of priority level 7 are accepted. In
this state the CPU does not increment the IFF even if
the CPU accepts an interrupt request of level 7.
(4) Software interrupt
The CPU accepts a software interrupt request during
DI status (IFF = 7) because the request has a priority
of level 7. The IFF is not changed by the software
interrupt.
Note:
(Level 7)
(Main)
(Main)
SWI3
NMI
[1], [2],……: Execution flow
[1]
[5]
[1]
[5]
DI
DI
(underline): Instruction
IFF ← 7
IFF ← 7
(NMI routine)
(SWI3 routine)
[2]
[4]
[2]
[4]
RETI
RETI
[3]
[3]
TMP93CS20
2004-02-10