TMP93xy20FG Toshiba, TMP93xy20FG Datasheet
TMP93xy20FG
Specifications of TMP93xy20FG
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TMP93xy20FG Summary of contents
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... TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L Series TMP93CS20 Semiconductor Company ...
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... Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = ( ...
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... The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. ...
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Serial interface: 2 channels • UART/synchronous mode: 1 channel • UART: 1 channel (9) Serial bus interface: 1 channel • bus mode/clock-synchronous 8-bit SIO mode 2 (10) 10-bit AD converter: 8 channels (11) Large current drive port: ...
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ADTRG AN0 to AN7 (P50 to P57) 10-bit 8-channel AVCC AD AVSS converter VREFH VREFL SCK (P60) Serial bus SO/SDA (P61) interface SI/SCL (P62) TXD0 (P63) Serial I/O RXD0 (P64) (Channel 0) SCLK0/ (P65) CTS 0 TXD1 (P80) Serial ...
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Pin Assignment and Functions The assignment of input and output pins for the TMP93CS20, their names and functions are described below. 2.1 Pin Assignment Figure 2.1.1 shows pin assignment of the TMP93CS20F. 108 109 (SEG34) PA2 105 110 (SEG35) ...
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Pin Names and Functions The names of the input/output pins and their functions are described below. Table 2.2.1 shows pin names and functions. Table 2.2.1 Pin Names and Function (1/3) Number of Pin Names I/O Pins P00 to P07 ...
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Table 2.2.1 Pin Names and Function (2/3) Number of Pin Name I/O Pins P50 to P57 8 Input AN0 to AN7 Input P60 1 I/O SCK I/O P61 1 I/O SO Output SDA I/O P62 1 I/O SI Input SCL ...
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Table 2.2.1 Pin Names and Function (3/3) Number of Pin Name I/O Pins P80 1 I/O TXD1 Output P81 1 I/O RXD1 Input P82 1 I/O TI2 Input P83 1 I/O TO3 Output P84 1 I/O Input WAIT P85 1 ...
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Operation This section describes in blocks the functions and basic operations of TMP93CS20 device. Please also refer to section 7., “Points to Note and Restrictions”, which describes some points requiring careful attention. 3.1 CPU TMP93CS20 devices have a built-in ...
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Figure 3.1.1 TMP93CS20 Reset Timing Chart 93CS20-9 TMP93CS20 2004-02-10 ...
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Memory Map Figure 3.2 memory map of the TMP93CS20. 000000H Internal I/O (128 bytes) 0000A0H 000100H Internal RAM (2 Kbytes) 0008A0H External area 010000H FF0000H Internal ROM (64 Kbytes) FFFF00H Vector table area (256 bytes) FFFFFFH Direct ...
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Dual Clock, Standby Function Dual clock, standby control circuits are comprised of a system clock controller, prescaler clock controller, internal clock pin output function and standby controller. The oscillator operating modes are classified as either (a) single clock mode ...
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Table 3.3.1 Relations between System Clock States and other Internal Operations Oscillator Operating Mode High Frequency (fc) Frequency (fs) Reset NORMAL Oscillation RUN IDLE2 IDLE1 STOP Stop Reset Oscillation NORMAL SLOW Programmable RUN Oscillator being used as system Clock: Oscillation ...
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Figure 3.3.2 Block Diagram of Dual Clock and Standby Circuits 93CS20-13 TMP93CS20 2004-02-10 ...
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SYSCR0 Bit symbol XEN XTEN (006EH) Read/Write After reset 1 0 Function High- Low- frequency frequency oscillator (fc) oscillator (fs) 0: Stop 0: Stop 1: Oscillation 1: Oscillation SYSCR1 Bit symbol (006FH) Read/Write After reset Function CKOCR Bit ...
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System Clock Controller The system clock controller generates the system clock signal (f internal I/O. It contains two oscillation circuits and a clock gear circuit for high frequency (fc). The register SYSCR1<SYSCK> changes the system clock to either fc ...
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Switching between normal and slow mode When the resonator is connected to the X1 and X2 the XT1 and XT2 pins, the warm-up timer is used to change the operation frequency after stable oscillation is attained. The ...
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Clock setting example 1: Changing from high frequency (fc) to low frequency (fs). SYSCR0 EQU 006EH SYSCR1 EQU 006FH WDCR EQU 005DH WDMOD EQU 005CH RES 7, (WDMOD) LD (WDCR), B1H SET 4, (WDMOD) SET 6, (SYSCR0) SET 2, (SYSCR0) ...
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Clock setting example 2: Changing from low frequency (fs) to high frequency (fc). SYSCR0 EQU 006EH SYSCR1 EQU 006FH WDCR EQU 005DH WDMOD EQU 005CH RES 7, (WDMOD) LD (WDCR), B1H RES 4, (WDMOD) SET 7, (SYSCR0) SET 2, (SYSCR0) ...
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Clock gear controller When the high-frequency clock fc is selected at SYSCR1<SYSCK> the clock gear select register SYSCR1<GEAR2:0> sets f Switching f with the clock gear reduces the power consumption. FPH Clock setting example 3: Changing gear ...
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Prescaler Clock Controller The 9-bit prescaler provides a clock signal to the 8-bit timers 16-bit timer 4, timer 6, timer 8, and timer A, and serial interface 0 and serial interface 1. The clock input to ...
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Standby Controller (1) HALT mode When the HALT instruction is executed, the operating mode changes to RUN, IDLE2, IDLE1, or STOP mode depending on the contents of the HALT mode setting register WDMOD<HALTM1:0>. Figure 3.3.5 shows the alternative states ...
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Table 3.3.5 I/O Operation during HALT Mode HALT mode WDMOD<HALTM1:0> CPU I/O Port 8-bit timer 16-bit timer Timer for realtime clock Serial channel Serial bus interface controller AD converter Watchdog timer Interrupt controller (2) How to release the HALT mode ...
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When the HALT mode is released by resetting, the internal RAM data maintains the state it was in before the HALT instruction was executed. However the other ...
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Operation 1. RUN mode In the RUN mode, the system clock in the MCU continues to operate even after a HALT instruction is executed. Only the CPU stops executing further instructions. In the halt state, an interrupt request is ...
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IDLE1 mode In the IDLE1 mode, the internal oscillator and the timer for realtime clock operates. The system clock in the MCU stops, and the CLK pin is fixed at the level “H” in the output enabled state. (CKOCR<CLKEN> ...
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STOP mode The STOP mode is selected to stop all internal circuits including the internal oscillator. The pin status in the STOP mode depends on the setting of a bit in the watchdog timer mode register WDMOD<DRVE>. (See Figure ...
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How to calculate the warm-up time WDMOD<WARM> Clock operation frequency after the 2 WDMOD<WARM> Clock operation frequency after the 2 The selection of normal versus SLOW modes is possible after the STOP mode is released. This ...
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Table 3.3.8 Pin States in STOP Mode Pin Name P00 to P07 Input/Output mode Output mode AD8 to AD15 P10 to P17 Input/Output mode Output mode AD0 to AD7 P20 to P27 Input mode Output mode A7/A16 to ...
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Input: Input gate in operation. Fix input voltage to low or high so that the input state pin stays constant. Output: Output state Output*: Open-drain output state. Input gate in operation. Set output to low or attach pull up ...
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Interrupts Interrupts are controlled by the CPU interrupt mask register SR<IFF2:0> and the built-in interrupt controller. Altogether the TMP93CS20 has the following 45 interrupt sources: • Interrupts from the CPU, 9 sources (Software interrupts, and illegal (Undefined) instruction execution) ...
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Interrupt processing Read interrupt vector V. clear interrupt request flag. Vector V = Micro DMA start vector? Internal operation PUSH PC General- PUSH SR purpose SR<IFF2:0> ← Accepted interrupt interrupt level + 1 processing INTNEST ← INTNEST + 1 PC ...
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General-purpose Interrupt Processing When accepting an interrupt, the CPU operates as follows. In the cases of software interrupts or interrupts generated by the CPU because of attempts to execute illegal instructions, the following steps (1) and (3) are not ...
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Maskable interrupt (INTT0 interrupt routine) (Main IFF ← 2 [1] [2] INTT0 [3] (Level 1) [4] RETI [5] IFF ← 1 During execution of the main program, the CPU accepts an interrupt request. The CPU then increments ...
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The addresses FFFF00H to FFFFFFH (256 bytes) of the TMP93CS20 are assigned as interrupt vector areas. Table 3.4.1 TMP93CS20 Interrupt Table Default Type Interrupt Source Priority 1 Reset, or SWI0 instruction 2 SWI 1 instruction 3 Illegal instruction, or SWI2 ...
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Setting to reset and interrupt vectors 1. Reset vector FFFF00H FFFF01H FFFF02H FFFF03H The vector base addresses are dependent on the products. Vector Base PC Setting Sequence Type No. Address after Reset TMP93CS44 PC<7:0> ← TMP93CS45 Data in location FFFF00H ...
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Setting example: Set the reset vector to FF0000H, 123456H. ORG FFFF00H DL FF0000H ORG FFFF20H DL FF9ABCH ORG FFFFA8H DL 123456H ORG FF0000H ORG FF9ABCH ORG 123456H 93CS20-36 vector to FF9ABCH ...
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Micro DMA In addition to the conventional interrupt processing, the TMP93CS20 also has a micro DMA function. When an interrupt is accepted, in addition to an interrupt vector, the CPU receives data indicating whether processed ...
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Figure 3.4.2 Micro DMA Cycle (COUNT ≠ 0) 93CS20-38 TMP93CS20 2004-02-10 ...
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Figure 3.4.3 Micro DMA Cycle (COUNT = 0) 93CS20-39 TMP93CS20 2004-02-10 ...
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Register configuration (CPU control registers) Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 Channel 1 DMAS1 DMAD1 DMAC1 DMAM1 Channel 2 DMAS2 DMAD2 DMAC2 DMAM2 Channel 3 DMAS3 DMAD3 DMAC3 DMAM3 8 bits 16 bits 32 bits These control registers can ...
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Transfer mode register details Mode Note: When setting values for this register, set the upper 4 bits Byte transfer Word transfer Transfer destination address ...
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Interrupt Controller Figure 3.4 block diagram of the interrupt circuits. The left half of the diagram shows the interrupt controller; the right half includes the CPU interrupt request signal circuit and the halt release signal circuit. Each ...
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Figure 3.4.4 Block Diagram of Interrupt Controller 93CS20-43 TMP93CS20 2004-02-10 ...
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Interrupt priority setting register Symbol Address 7 6 INTAD IADC IADM2 INTE0AD 0070H R INT2 I2C I2M2 INTE21 0071H R INT4 I4C I4M2 INTE43 0072H R INT9 I9C I9M2 INTE98 0073H R/W 0 ...
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Symbol Address 7 6 INTTR5 (TREG5) IT5C IT5M2 INTET54 007AH R INTTR7 (TREG7) IT7C IT7M2 INTET76 0044H R INTTR9 (TREG9) IT9C IT9M2 INTET98 0045H R INTTRB (TREGB) ITBC ITBM2 INTETBA 0046H R ...
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External interrupt control 7 IIMC Bit symbol I7FE I4FE (007BH) Read/Write After reset 0 Read- INT7 0: INT4 Function 0: modify- rising rising write is edge edge prohibited INT7 1: INT4 1: falling falling edge edge Note 1: This ...
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Table 3.4.2 Setting of External Interrupt Pin Function Interrupt Pin Name P77 NMI INT0 P33 INT1 P34 INT2 P35 INT3 P36 INT4 P37 INT7 P66/TI0 INT8 P70 INT9 P71 INTA P74 INTB P75 Mode Setting Method IIMC<NMIREE> P7FC<NMIC> ...
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Micro DMA start vector When the CPU reads the interrupt vector after accepting an interrupt, it simultaneously compares the interrupt vector with each channel’s micro DMA start vector (Bits the interrupt vector). When the two ...
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Notes The instruction execution unit and the bus interface unit of this CPU operate independently of each other. Therefore, if the instruction used to clear the interrupt request flag of an interrupt is fetched before the interrupt is generated, ...
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Functions of Ports The TMP93CS20 has 88 bits for I/O ports. These port pins have I/O functions for the built-in CPU and internal I/Os as well as general-purpose I/O port functions. Table 3.5.1 lists the function of each port ...
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Table 3.5.2 I/O Registers and Specifications (1/2) Port No. Pin No. Port 0 P00 to P07 Input port Output port AD0 to AD7 bus Port 1 P10 to P17 Input port Output port AD8 to AD15 bus A8 to A15 ...
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Table 3.5.2 I/O Registers and Specifications (2/2) Port No. Pin No. Port 5 P50 to P57 Input port AN0 to AN7 input (Note 2) Port 6 P60 to P67 Input port Output port P60 SCK input SCK output P61 SO ...
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Port 0 (P00 to P07) Port 8-bit general-purpose I/O port. I/O can be set on a bit basis using the control register P0CR. Resetting resets all bits of P0CR to 0 and sets port 0 to ...
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Port 1 (P10 to P17) Port 8-bit general-purpose I/O port. I/O can be set on a bit basis using control register P1CR and function register P1FC. Resetting resets all bits of output latch P1, control register ...
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Bit symbol P07 P06 P0 (0000H) Read/Write After reset 7 6 P0CR Bit symbol P07C P06C (0002H) Read/Write After reset 0 0 Function 0:Input 1:Output (when externally accessed, port 0 becomes AD7 to AD0 and P0CR is cleared ...
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Port 2 (P20 to P27) Port 8-bit general-purpose I/O port. I/O can be set on a bit basis using the control register P2CR and function register P2FC. Resetting resets all bits of output latch P2 to ...
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P2 Bit symbol P27 P26 (0006H) Read/Write After reset 7 6 Bit symbol P27C P26C P2CR (0008H) Read/Write After reset 0 0 Function 7 6 Bit symbol P27F P26F P2FC (0009H) Read/Write After reset 0 0 Function Note ...
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Port 3 (P30 to P37) Port 8-bit general-purpose I/O port. I/O can be set on a bit basis, but note that P30 and P31 are used for output only. I/O is set using control register P3CR ...
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P32 ( ) HWR Reset Direction control (on bit basis) P3CR write Function control (on bit basis) P3FC write S Output latch P3 write S Selector P3 read (3) P33 (INT0) Reset Direction control (on bit basis) P3CR write ...
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P34 (INT1), P35 (INT2), P36 (INT3), P37 (INT4/ Reset Direction control (on bit basis) P3CR write Output latch P3 write S Selector P3 read INT1 to INT4 P3FC <I1IE> IIMC <I1FE> <I2IE> <I3IE> <I4IE> ADTRG Only P37 has this ...
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Bit symbol P37 P36 P3 (0007H) Read/Write After reset Bit symbol P37C P36C P3CR (000AH) Read/Write After reset 0 0 Function 7 6 Bit symbol I4IE I3IE P3FC (000BH) Read/Write After reset 0 0 ...
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Port 4 (P40 to P47) Port 8-bit general-purpose I/O port. I/O can be set on a bit basis. Resetting sets port input port and connects a pull-up resistor. It also sets all bits ...
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Port 41, 43 (TO4/KEY1, TO6/KEY3) Port general-purpose I/O port, and is also used as an output TO4 and KEY1 of a 16-bit timer 4. Port general-purpose I/O port, and is also used as ...
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Port (KEY4 to KEY7) Port are general-purpose I/O ports, and are also used as KEY4 to KEY7. Reset Direction control (on bit basis) P4CR write S Output latch P4 write Selector P4 read ...
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Bit symbol P47 P46 P4 (000CH) Read/Write After reset Bit symbol P47C P46C P4CR (000EH) Read/Write After reset 0 0 Function 7 6 Bit symbol P4FC (0010H) Read/Write After reset Function Note 1: Read-modify-write ...
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Port 5 (P50 to P57) Port 8-bit input port, also used as an analog input pin for the internal AD converter. Port 5 read AD read 7 6 Bit symbol P57 P56 P5 (000DH) Read/Write After ...
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Port 6 (P60 to P67) Port are 8-bit general-purpose I/O ports. I/O can be set on a bit basis. In addition to functioning as general-purpose I/O ports, port also function as serial bus ...
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Port 61, 62, and 63 (SO/SDA, SI/SCL, TXD0) In addition to functioning as a general-purpose I/O port, port 61 also functions output pin when the serial bus interface is in the SIO mode, and a SDA ...
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Port 66, 67 (TI0/INT7, TO1) In addition to functioning as a general-purpose I/O port, port 66 also functions as an event count input TI0 of the timer 0 and an external interrupt request input INT7. Port ...
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Bit symbol P67 P66 P6 Read/Write (0012H) After reset Bit symbol P67C P66C P6CR Read/Write (0014H) After reset 0 0 Function 7 6 Bit symbol P67F I7IE P6FC (0016H) Read/Write W After reset 0 ...
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Port 7 (P70 to P77) Port 8-bit general-purpose I/O port. I/O can be set on a bit basis. Resetting sets port input port and connects a pull-up resistor. In addition to functioning as ...
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When using INT8 to INTB interrupts: When a general-purpose I/O port or a timer event count input is used during using INT8 to INTB interrupt functions, an interrupt request occurs at the rising and the falling edges of these I/O ...
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P77 ( ) NMI P77 is a general-purpose I/O port, and is also used as a non-maskable interrupt ( ) input pin. The pin is set by the function register P7FC<NMIC>. Writing NMI NMI NMIC to 1 sets input ...
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Bit symbol P77 P76 P7 (0013H) Read/Write After reset Bit symbol P77C P76C P7CR (0015H) Read/Write After reset 0 0 Function 7 6 Bit symbol NMIC P76F P7FC (0017H) Read/Write R/W W After reset ...
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Port 8 (P80 to P87) • Port Port are 6-bit general-purpose I/O ports. I/O can be set on a bit basis. Resetting sets port input ports. All bits of ...
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Port 81, 82 (RXD1, TI2) In addition to functioning as I/O ports, port 81 and 82 also function as RXD1 input pin of the serial channel 1 and input TI2 pin of an 8-bit timer. These ports are also ...
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Port 86 (XT1), 87 (XT2) In addition to functioning as I/O ports, port 86 and 87 also function as low-frequency oscillator serial pins. Reset S BUS6 Direction control (on bit basis) P8CR write S BUS6 Output latch P8 write ...
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Bit symbol P87 P86 P8 (0018H) Read/Write After reset 1 1 Output mode 7 6 Bit symbol P87C P86C P8CR (001AH) Read/Write After reset 1 1 Function 7 6 Bit symbol P8FC (001CH) Read/Write After reset Function Note ...
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Port 9 (P90 to P97), Port A (PA0 to PA7) Port 9 and port A are 8-bit open-drain output ports. In addition to functioning as output ports, port 9 and port A also function as segment outputs of the ...
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Bit symbol P97 P96 P9 (0019H) Read/Write After reset Bit symbol PA7 PA6 PA (001EH) Read/Write After reset Bit symbol P97F P96F P9FC (001DH) Read/Write After reset 0 0 Function ...
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Bus Width/Wait Controller The TMP93CS20 has a built-in bus width/wait controller used to control chip select, wait ( pin), and data bus size ( bits) for any of the three block address areas. WAIT 3.6.1 Address/Data Bus ...
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Bus Width/Wait Control Registers Table 3.6.1 shows control registers. One block of the address areas is controlled by each of the 1-byte bus width/wait control registers WAITC0, WAITC1, and WAITC2. (1) Data bus size select Bit4 (B0BUS, B1BUS, and ...
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Table 3.6.1 Bus Width Control Register 7 6 WAITC0 Bit symbol (0068H) Read/Write After reset Function Bit symbol WAITC1 (0069H) Read/Write After reset Function Bit symbol WAITC2 (006AH) Read/Write After reset Function Note: Read-modify-write is prohibited for WAITC0, WAITC1, and ...
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Bus Width/Wait Control An image of the actual addresses which can be specified by chip select is shown below. Out of the whole memory area, address areas that can be specified are divided into four parts. Addresses from 000000H ...
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Example of Usage Figure 3.6 example in which an external memory is connected to the TMP93CS20. In this example, a 128-Kbyte ROM is connected using a 16-bit bus, and a 256 Kbyte RAM is connected using a 16-bit ...
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Timer The TMP93CS20 contains four 8-bit timers (timers 0 to 3), each of which can be operated independently. The cascade connection also allows these timers to be used together as two 16-bit timers. The following four operating modes ...
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Figure 3.7.1 Block Diagram of 8-Bit Timers (Timers 0 and 1) 93CS20-87 TMP93CS20 2004-02-10 ...
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Figure 3.7.2 Block Diagram of 8-Bit Timers (Timers 2 and 3) 93CS20-88 TMP93CS20 2004-02-10 ...
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Prescaler There are 9-bit prescaler and prescaler clock selection registers to generate input clock signals for the 8-bit timers the 16-bit timers and A, and the serial interfaces 0 and 1. Figure 3.7.3 ...
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The timer clock selected among f prescaler. The selection is made by system clock control register SYSCR0<PRCK1:0>. Resetting sets <PRCK1:0> to 00, which selects the f The 8-bit timers 0 and 1 select among 4 clock inputs: φT1, φT4, φT16, ...
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Timer registers These are 8-bit registers for setting a time interval. When the values of the timer registers match the values of the corresponding up counters, the comparator match detect signal becomes active. If the set value is 00H, ...
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Comparator A comparator compares the value in the up counter with the values to which the timer register is set. When they match, the up counter is cleared to 0 and an interrupt signal (INTT0, INTT1, INTT2, and INTT3) ...
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TRUN Bit symbol PRRUN (0020H) Read/Write R/W After reset 0 Function Note: TRUN<Bit6> is read SYSCR0 Bit symbol XEN XTEN (006EH) Read/Write After reset 1 0 Function High- Low- frequency frequency oscillator oscillator (fc) ...
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Timer 1 and Timer 0 Mode Control Register 7 6 Bit symbol T10M1 T10M0 T10MOD (0024H) Read/Write After reset 0 0 Function Operation mode 00: 8-bit timer 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM Figure 3.7.6 Registers for ...
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Timer 3 and Timer 2 Mode Control Register 7 6 T32MOD Bit symbol T32M1 T32M0 (0028H) Read/Write After reset 0 0 Function Operation mode 00: 8-bit timer 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM Figure 3.7.7 Registers for ...
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TFFCR Bit symbol TFF3C1 TFF3C0 (0025H) Read/Write W After reset 1 1 Function 00: Invert TFF3 01: Set TFF3 10: Clear TFF3 11: Don’t care Select inverse signal of timer F/F3 (TFF3) (“Don’t care” except in 8-bit timer ...
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Timer Register Double Buffer Control Register 7 6 TRDC Bit symbol (0029H) Read/Write After reset Function Figure 3.7.9 Registers for 8-Bit Timers (5/ Control of timer register double buffer 0 1 93CS20-97 TMP93CS20 1 0 TR2DE ...
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The operation of 8-bit timers will be described below: (1) 8-bit timer mode Four interval timers, designated can be used independently as 8-bit interval timers. When setting functions and count data, stop operation of timer 0 to ...
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TO3 pin MHz, set each register by the following Example: To output a 2.4 procedures. Either timer 2 or timer 3 may be used, but this example uses timer ...
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Making timer 1 count up by matching the signal from the timer 0 comparator. (Same function is achieved by using timer 3 and timer 2.) Set the 8-bit timer mode, and set the comparator output of timer 0 as ...
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The comparator signal is output from timer 2 each time the up-counter UC2 matches TREG2, when the up counter UC2 is not to be cleared. With the timer 3 comparator, the match detect signal is output at each comparator check ...
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TI2 φT1 Selector φT4 φT16 T32MOD<T2CLK1:0> Comparator TREG2 Selector Shift trigger TREG2-WR Register buffer TRDC<TR2DE> Figure 3.7.14 Block Diagram of 8-Bit PPG Output Mode When the double buffer of TREG2 is enabled in this mode, the value of the register ...
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Calculate the value to be set in the timer register. To obtain a frequency of 62.5 kHz, the pulse cycle time t should be 1/62.5 kHz = 16 µs. Given φT1 = 0.4 µs (at 20 MHz), ...
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PWM output mode This mode is valid only for timer 0 and timer 2. In this mode, the maximum 8-bit resolution of the PWM pulse can be output. When using timer 0, the PWM pulse is output to ...
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In this mode, the value of the register buffer will be shifted into TREG2 overflow is detected while the double buffer of TREG2 is enabled. Use of the double buffer makes easy the handling of small-duty waves. ...
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Select Select Gear Value System Prescaler Clock <GEAR2:0> Clock <PRCK1:0> <SYSCK> 1 (fs) XXX 000 (fc) 001 (fc/ (fc) 010 (fc/4) FPH 011 (fc/8) 100 (fc/16) 01 XXX (Low-frequency XXX clock) 10 XXX XXX (fc/16 clock) ...
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Timer/Event Counter The TMP93CS20 contain four multifunctional 16-bit timer/event counters (Timers and A) which support the following operation modes. • 16-bit interval timer mode • 16-bit event counter mode • 16-bit programmable pulse generation (PPG) ...
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Figure 3.8.1 Block Diagram of 16-Bit Timer (Timer 4) 93CS20-108 TMP93CS20 2004-02-10 ...
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Figure 3.8.2 Block Diagram of 16-Bit Timer (Timer 6) 93CS20-109 TMP93CS20 2004-02-10 ...
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Bit symbol T4MOD (002EH) Read/Write After reset Function Figure 3.8.3 Registers for 16-Bit Timer/Event Counter (1/6) Timer 4 Mode Control Register − − CAP4IN Control of Write “0”. Control of software ...
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Bit symbol T4FFCR (002FH) Read/Write After reset Function Figure 3.8.4 Registers for 16-Bit Timer/Event Counter (2/6) Timer 4 Flip-flop Control Register − − EQ5T4 R/W R/W R Write “0”. Write “0”. TFF4 ...
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Bit symbol T6MOD (0036H) Read/Write After reset Function Figure 3.8.5 Registers for 16-Bit Timer/Event Counter (3/6) Timer 6 Flip-flop Control Register − − CAP6IN Control of Write “0”. software capture 0: ...
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Bit symbol T6FFCR (0037H) Read/Write After reset Function Figure 3.8.6 Reigsters for 16-Bit Timer/Event Counter (4/6) Timer 6 Flip-flop Control Register − − EQ7T6 R/W R/W R Write “0”. Write “0”. TFF6 ...
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Bit symbol QCU T16CR (003AH) Read/Write R/W After reset 0 Function Warm-up timer control Note 1: In case of not using the 7 stage binary counter as a warm-up timer, a stable clock signal must be input from ...
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Bit symbol PRRUN TRUN (0020H) Read/Write R/W After reset 0 Function Note: TRUN<Bit6> is always read SYSCR0 Bit symbol XEN XTEN (006EH) Read/Write After reset 1 0 Function High- Low- frequency frequency oscillator oscillator ...
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Prescaler There are 9-bit prescaler and prescaler clock-selection registers to generate input clock signals for 8-bit timers 16-bit timers and A, and serial interfaces 0 and 1. Figure 3.8.9 shows the block diagram. ...
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The clock selected from among f prescaler. This selection is made by prescaler clock selection register SYSCR0 <PRCK1:0>. Resetting sets <PRCK1:0> to 00, selecting the f The 16-bit timers 4 and 6 select among 3 clock inputs: φT1, φT4, and ...
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The TREG4 timer register is a double buffer structure, which is paired with a register buffer. The timer control register T16CR<DB4EN> controls whether the double buffer structure should be enabled or disabled disabled when <DB4EN> and ...
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Generating interrupts at fixed intervals: In this example, the interval time is set in the timer register TREG5 to generate the interrupt INTTR5 ← − X − ...
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Square wave pulse can be generated at any frequency and duty by timer 4. The output pulse may be either low-active or high-active. Timer 4 outputs a pulse to the TO4 pin. ...
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Figure 3.8.12 shows the block diagram of this mode. TI4 φT1 Selector φT4 φT16 16-bit comparator TREG4 Selector TREG4-WR Register buffer 4 T16CR<DB4EN> Figure 3.8.12 Block Diagram of 16-Bit PPG Mode ← ...
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Timer/Event Counter 8 and A Each of timer/event counter 8 and A consists of a 16-bit up counter, two 16-bit timer registers (One with a double buffer), two 16-bit capture registers, two comparators, a capture input controller, a ...
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Figure 3.8.13 Block Diagram of 16-Bit Timer (Timer 8) 93CS20-123 TMP93CS20 2004-02-10 ...
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Figure 3.8.14 Block Diagram of 16-Bit Timer (Timer A) 93CS20-124 TMP93CS20 2004-02-10 ...
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Bit symbol T8MOD (0038H) Read/Write After reset Function Figure 3.8.15 Registers for 16-Bit Timer/Event Counter (1/4) Timer 8 Mode Control Register CAP8IN CAP89M1 CAP89M0 Capture timing Control of Control of timer ...
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Bit symbol T8FFCR (0039H) Read/Write After reset Function Figure 3.8.16 Registers for 16-Bit Timer/Event Counter (2/4) Timer 8 Flip-flop Control Register CAP9T8 CAP8T8 EQ9T8 R TFF8 invert trigger 0: Disable trigger 1: ...
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Bit symbol TAMOD (0048H) Read/Write After reset Function Figure 3.8.17 Registers for 16-Bit Timer/Event Counter (3/4) Timer A Mode Control Register CAPAIN CAPABM1 CAPABM0 Control of Control of Capture timing timer ...
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Bit symbol TAFFCR (0049H) Read/Write After reset Function Figure 3.8.18 Registers for 16-Bit Timer/Event Counter (4/4) The 16-bit timer control register, the timer operation control register, and the system clock control registers operate in the same way as ...
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Prescaler and (2) Up counter have the same configuration as that of the timer/event counter 4 and 6 described in section 3.8.1. (3) Timer register These two 16-bit registers are used to set the interval time. When the value ...
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Capture input control This circuit controls the timing of latching the value of up counter UC8 into CAP8 and CAP9. The latch timing of the capture register is controlled by register T8MOD<CAP89M1:0>. There are four possible settings: • When ...
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Generating interrupts at fixed intervals: In this example, the interval time is set in the timer register TREG9 to generate the interrupt INTTR9 ← − X − ...
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Square wave pulse can be generated at any frequency and duty by timer 8. The output pulse may be either low-active or high-active. The PPG mode is obtained by inversion of the ...
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Figure 3.8.21 shows the block diagram of this mode. TI8 φT1 Selector φT4 φT16 16-bit comparator TREG8 Selector TREG8-WR Register buffer 8 T16CR<DB8EN> Figure 3.8.21 Block Diagram of 16-Bit PPG Mode ← ...
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Application examples of the capture function Used capture function, they can be applied in many ways, for example: 1. One-shot pulse output from external trigger pulse 2. Frequency measurement 3. Pulse width measurement 4. Time difference measurement These four ...
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Setting example: To output one-shot pulse to the external trigger pulse from TI8 pin, with 3 ms delay * Clock condition Main setting ← − − T8MOD ← ...
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Count clock (Internal clock) c TI8 pin input (External trigger pulse) INT8 occurrence. Load the up counter value into capture register 8 (CAP8). Match with TREG9 Enable inversion Timer output pin TO8 Pulse width Enable inversion caused by loading of ...
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Pulse width measurement This mode allows measurement of the H level width of an external pulse. While keeping the 16-bit up counter UC8 counting (Free running) with the internal clock input, the external pulse is input via the TI8 ...
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Time difference measurement This mode is used to measure the difference in time between the rising edges of external pulses input. While keeping the 16-bit up counter UC8 counting (Free running) with the internal clock, the UC8 value is ...
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Serial Channel TMP93CS20 contains 2 serial I/O channels. Channel 0 select UART mode (Asynchronous transmission) or I/O interface mode (Synchronous transmission). Channel 1 is used only in UART mode. The serial channel has the following operation modes. • I/O ...
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Mode 0 (I/O interface mode) Bit0 1 2 Transfer direction • Mode 1 (7-bit UART mode) No parity Start Bit0 1 Parity Start Bit0 1 • Mode 2 (8-bit UART mode) No parity Start Bit0 1 Parity Start Bit0 ...
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The serial channel has buffer registers for transmitting and receiving operations in order to temporarily store transmitted or received data. This is done so that transmitting and receiving operations can be done independently (Full duplex). However, in I/O interface mode, ...
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Bit symbol TB8 CTSE SC0MOD (0052H) Read/Write After reset Undefined 0 Function Transfer Hand data bit8 shake 0: CTS disable 1: CTS enable Figure 3.9.2 Serial Mode Control Register (Channel 0, SC0MOD RXE WU SM1 ...
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SC0CR Bit symbol RB8 EVEN (0051H) Read/Write R After reset Undefined 0 Function Received Parity data bit8 0: Odd 1: Even Note 1: To use baud rate generator, set TRUN<PRRUN> putting the prescaler in RUN mode. ...
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BR0CR Bit symbol BR0ADD (0053H) Read/Write After reset (16 − K)/16 Function Always fixed to 0 division 0: Disable 1: Enable + (16 − K)/16 division enable 0 Disable 1 Enable 7 6 Bit ...
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TB7 TB6 TB5 TB4 SC0BUF (0050H RB7 RB6 RB5 RB4 Note: Prohibit read-modify-write for SC0BUF. Figure 3.9.5 Serial Transmission/Receiving Buffer Registers (Channel 0, BR0CR) 93CS20-145 (Transmission) TB3 TB2 ...
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SC1MOD Bit symbol TB8 (0056H) Read/Write After reset Undefined 0 Function Transferred Fix at “0” data bit8 Figure 3.9.6 Serial Mode Control Register (Channel 1, SC1MOD RXE WU SM1 SM0 R ...
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SC1CR Bit symbol RB8 EVEN (0055H) Read/Write R After reset Undefined 0 Function Received Parity data bit8 0:Odd 1:Even Note: As all error flags are cleared after reading, do not test only a single bit with a bit-testing ...
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BR1CR Bit symbol BR1ADD (0057H) Read/Write After reset (16 − K)/16 Function Always fixed to 0 division 0: Disable 1: Enable + (16 − K)/16 division enable 0 Disable 1 Enable 7 6 BRADD1 ...
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TB7 TB6 SC1BUF (0054H RB7 RB6 Note: Prohibit read-modify-write for SC1BUF. Figure 3.9.9 Serial Transmission/Receiving Buffer Registers (Channel 1, SC1BUF P6FC Bit symbol P67F I7IE (0016H) Read/Write W W After reset 0 0 Function ...
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P8FC Bit symbol (001CH) Read/Write After reset Function Prohibit read-modify-write. Figure 3.9.12 Port 8 Function Register (P8FC P8ODE Bit symbol (0021H) Read/Write After reset Function Note: P8ODE<Bit7:6> is read as 1. Figure 3.9.13 Port 8 Open-drain ...
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Configuration Figure 3.9.14 shows the block diagram of the serial channel 0. Serial clock generation circuit BR0CR<BR0CK1:0> BR0CR <BR0S3:0> φT0 φT2 φT8 φT32 BR0CR <BR0ADD> Baud rate generator System clock f (φ1) SYS SCLK0 (Shared by P65) I/O ...
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Figure 3.9.15 shows the block diagram of the serial channel 1. Serial clock generation circuit BR1CR<BR1CK1:0> BR1CR <BR1S3:0> φT0 φT2 φT8 φT32 BR0CR <BR1ADD> Baud rate generator System clock f (φ1) SYS Receive counter SC1MOD (÷ 16) RXDCLK SC1MOD<RXE> Receive ...
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Prescaler, prescaler clock select There are 9-bit prescaler and prescaler clock selection registers to generate input clock for 8-bit timers 16-bit timer/event counters and A and serial interfaces 0, 1. Figure 3.9.16 shows ...
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The clock selected among f FPH input to this prescaler. This is selected by prescaler clock selection register SYSCR0<PRCK1:0>. Resetting sets <PRCK1:0> and selects the f The baud rate generator selects between 4 clock inputs: φT0, φT2, φT8, ...
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Integer divisor (N divisor) For example, when the source clock (fc) is 12.288 MHz, the input clock is φT2 (fc/16), and frequency divisor is N(BR0CR<BR0S3:0> BR0CR<BRADD0> the baud rate in UART mode becomes as follows: ...
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Table 3.9.2 Selection of Transfer Rate (when baud rate generator is used) Input Clock fc [MHz] Frequency Divisor 2 4 9.830400 12.288000 A 3 14.745600 6 C Note 1: Transfer rates in I/O interface mode are 8 ...
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Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. • I/O interface mode When in SCLK output mode with the setting of SC0CR<IOC> the basic clock will be generated by dividing ...
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Receiving buffer To prevent an overrun error, the receiving buffer has a double buffer structure. Received data is stored bit by bit in receiving buffer 1 (Shift register type). When 7 bits or 8 bits of data are stored ...
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Handshake function Serial channel 0 has a frame, thus, overrun errors can be avoided. The handshake function is enabled/disabled by SC0MOD<CTSE>. When the CTS0 send is halted until the is generated, it requests the next data send to the CPU. ...
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Transmission buffer The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU from the least significant bit (LSB) in order. When all bits are shifted out, the transmission buffer becomes empty and generates INTTX0 ...
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Generating timing 1) UART mode Receiving Mode 9 Bits (Note) Interrupt timing Center of last bit (Bit8) Framing error timing Center of stop bit − Parity error timing Overrun error timing Center of last bit (Bit8) In 9-bit and ...
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Operational Description (1) Mode 0 (I/O interface mode) This mode is used to increase the number I/O pins for transmitting or receiving data to or from an external shifter register. This mode includes the SCLK output mode to ...
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Transmission In SCLK output mode, 8-bit data and synchronous clock are output from TXD0 pin and SCLK0 pin respectively, each time the CPU writes data to the transmission buffer. When all data is output, INTES0<ITX0C> will be set to ...
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Receiving In SCLK output mode, the synchronous clock is outputted from SCLK0 pin and the data is shifted to receiving buffer 1. This starts when the receive interrupt flag INTES0<IRX0C> is cleared by reading the received data. When 8-bit ...
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Mode 1 (7-bit UART mode) The 7-bit mode can be set by setting serial channel mode register SC0MOD<SM1:0> to 01. In this mode, a parity bit can be added, and the addition of the parity bit can be enabled ...
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Main setting ← − − − 0 − − − − P6CR ← − SC0MOD ← SC0CR ...
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Protocol 1. Select the 9-bit UART mode for the master and slave controllers. 2. Set SC0MOD<WU> bit of each slave controller enable data receiving. 3. The master controller transmits one-frame data including the 8-bit select code for ...
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Setting example: To link two slave controllers serially with the master controller, and use the internal clock φ1 as the transfer clock. TXD RXD TXD Master Since serial channels 0 and 1 operate in exactly the same way, channel 0 ...
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Serial Bus Interface (SBI) The TMP93CS20 has a 1-channel serial bus interface which employs a clocked-synchronous 8-bit serial bus interface and an I The serial bus interface is connected to an external device through P61 (SDA) and P62 (SCL) ...
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Serial Bus Interface (SBI) Control The following reginsters are used for control and operation status monitoring when using the serial bus interface (SBI). • Serial bus interface control register 1 (SBICR1) • Serial bus interface control register 2 (SBICR2) ...
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I C Bus Mode Control The following registers are used for control and operation status monitoring when using the serial bus interface (SBI) in the I Serial Bus Interface Control Register 1 7 Bit symbol BC2 BC1 SBICR1 ...
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Serial Bus Interface Control Register 2 7 Bit symbol MST TRX SBICR2 Read/Write W (R/W Note 1) (004EH) After reset 0 Prohibit Function Master/ Transmitter/ read- receiver modify- slave selection write selection Note 1: This register functions as the SBISR ...
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Serial Bus Interface Status Register 7 Bit symbol MST TRX SBISR Read/Write (004EH) After reset 0 Prohibit Function Master/ Transmitter read- slave /receiver modify- selection selection write status status monitor monitor Note: Bits this register function ...
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Serial Bus Interface Control Register 3 7 Bit symbol SBICR3 Read/Write (004FH) After reset Function Serial Bus Interface Data Buffer Register 7 Bit symbol DB7 SBIDBR Read/Write (004CH) Prohibit After reset read- modify- Note 1: When writing the send data, ...
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Acknowledge mode specification Set SBICR1<ACK> for operation in the acknowledge mode. The TMP93CS20 generates an additional clock pulse for an acknowledge signal when operating in the master mode. In the transmitter mode during the clock pulse cycle, ...
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Clock synchronization The I C bus has a clock synchronization function to meet the transfer speed slow processing device when a transfer is performed between devices which have different process speed. The clock synchronization functions when ...
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Transmitter/receiver selection Set SBICR2<TRX> for operating the TMP93CS20 as a transmitter. Set <TRX> for operation as a receiver. When data with an addressing format is transferred in the slave mode, when a slave address with ...
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Cancel interrupt service request When the TMP93CS20 is the master mode and transferring a number of clocks set by the SBICR1<BC2:0> and the SBICR1<ACK> is complete, a serial bus interface interrupt request (INTS2) is generated. In the slave mode, ...
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Slave address match detection monitor SBISR<AAS> is set the slave mode, in the address recognition mode (I2CAR<ALS> when receiving the GENERAL CALL or the slave address with the same value that is set to ...
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Data Transfer Bus Mode (1) Device initialization First, set SBICR1<ACK, SCK2:0>. Specify 0 to bits and 3 in the SBICR1. Set the slave address <SA6:0> and <ALS> to I2CAR (<ALS> ...
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One-word data transfer Test SBISR<MST> by the INTS2 interrupt process after a one-word data transfer is completed, and determine whether the mode is a master or slave. a. When <MST> (Master mode) Test SBISR<TRX> and determine whether ...
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When <TRX> (Receiver mode) When the next transmitted data is other than 8 bits, set SBICR1<BC2:0> again. Set <ACK> and read the received data from the SBIDBR to release the SCL line. The read data is ...
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When < MST> (Slave mode) In the slave mode, the TMP93CS20 operates either in normal slave mode or in recovery process after a noise detection. In the slave mode, an INTS2 interrupt request occurs when the serial ...
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Stop condition generation When SBISR<BB> sequence of generating a stop condition is started by writing 1 to SBICR2<MST, TRX, PIN>, and 0 to <BB>. Do not modify the contents of <MST, TRX, BB, PIN> until the ...
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Clock-synchronous 8-Bit SIO Mode Control The following registers are used for control and operation status monitoring when using the serial bus interface (SBI) in the clock-synchronous 8-bit SIO mode. Serial Bus Interface Control Register 1 7 Bit symbol ...
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Serial Bus Interface Control Register 2 7 Bit symbol SBICR2 Read/Write (004EH) After reset Function Prohibit read- modify- write Note 1: Switch a mode to port after data transfer is complete. Note 2: Switch a mode to SIO mode after ...
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Serial clock a. Clock source SBICR1<SCK2:0> are used to select the following functions. Internal clock In the internal clock mode, any of seven frequencies can be selected. The serial clock is output to the outside on the SCK pin. ...
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SCK pin SO pin Bit0 Bit1 76543210 * 7654321 ** 765432 *** 76543 **** 7654 ***** 765 ****** 76 Shift register SCK pin SO pin Bit0 Bit1 Shift register 0 ******* 10 ****** 210 ***** ******** *: Don't care Figure ...
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SCK pin (Output) SO pin INTS2 interrupt request a b SBIDBR Write transmitted data <SIOS> <SIOF> <SEF> SCK pin (Input) SO pin ...
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Set the control register to a receive mode and SBICR1<SIOS> for switching to the receive mode. Data is received from the SI pin to the shift register in synchronous with the serial clock, starting ...
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Set a control register to a transmit/receive mode and write data to the SBIDBR. After the data is written, set SBICR1<SIOS> start transmitting/receiving. When transmitting, the data is output from the SO pin ...
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SCK pin <SIOF> Bit6 Bit7 in last transmitted word SO pin Figure 3.10.27 Transmitted Data Hold Time at End of Transmit/Receive 93CS20-192 = Min 4/f t [s] (in NORMAL mode) SODH FPH TMP93CS20 2004-02-10 ...
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Analog/Digital Converter TMP93CS20 incorporate a high-speed, high-precision 10-bit analog/digital converter (AD converter) with 8-channel analog input. Figure 3.11 block diagram of the AD converter. The 8-channel analog input pins (AN0 to AN7) are also used as input ...
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Analog/Digital Converter Registers AD converter is controlled by two AD mode control registers (ADMOD0 and ADMOD1). AD conversion result is stored in eight AD conversion result registers (ADREG04H/L, ADREG15H/L, ADREG26H/L, ADREG37H/L ADMOD0 Bit symbol EOCF ADBF (005EH) ...
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ADMOD1 Bit symbol VREFON (005FH) Read/Write R/W After reset 1 Function String resistor 0: OFF 1: ON Note: Set the <VREFON> bit to 1 before starting conversion (before writing 1 to ADMOD0<ADS>). Figure 3.11.3 Register for AD Converter ...
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AD Conversion Result Register 0/4 Low 7 ADREG04L Bit symbol ADR01 ADR00 (0060H) Read/Write R After reset Undefined Function Stores lower 2 bits of AD conversion result. AD Conversion Result Register 0/4 High 7 ADREG04H Bit symbol ADR09 ADR08 (0061H) ...
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AD Conversion Result Register 2/6 Low 7 ADREG26L Bit symbol ADR21 ADR20 (0064H) Read/Write R After reset Undefined Function Stores lower 2 bits of AD conversion result. AD Conversion Result Register 2/6 High 7 ADREG26H Bit symbol ADR29 ADR28 (0065H) ...
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Operation (1) Analog reference voltage High analog reference voltage is applied to the VREFH pin, and low analog reference voltage is applied to the VREFL pin. The voltage between VREFH and VREFL is divided into 1024 increments using a ...