EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 432

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

15–2
Error Detection Fundamentals
Configuration Error Detection
User Mode Error Detection
Stratix III Device Handbook, Volume 1
1
Error detection determines if the data received through a medium is corrupted during
transmission. To accomplish this, the transmitter uses a function to calculate a
checksum value for the data and appends the checksum to the original data frame.
The receiver uses the same calculation methodology to generate a checksum for the
received data frame and compares the received checksum to the transmitted
checksum. If the two checksum values are equal, the received data frame is correct
and no data corruption occurred during transmission or storage.
The error detection CRC feature uses the same concept. When Stratix III devices have
been configured successfully and are in user mode, the error detection CRC feature
ensures the integrity of the configuration data.
There are two CRC error checks. One always runs during configuration, the second
optional CRC error check runs in the background in user mode. Both CRC error
checks use the same CRC polynomial but different error detection implementations.
For more information, refer to
Detection”.
In configuration mode, a frame-based CRC is stored within the configuration data
and contains the CRC value for each data frame.
During configuration, the Stratix III device calculates the CRC value based on the
frame of data that is received and compares it against the frame CRC value in the data
stream. Configuration continues until either the device detects an error or
configuration is complete.
In Stratix III devices, the CRC value is calculated during the configuration stage. A
parallel CRC engine generates 16 CRC check bits per frame and stores them into
CRAM. The CRAM chain used for storing CRC check bits is 16 bits wide; its length is
equal to the number of frames in the device.
Stratix III devices have built-in error detection circuitry to detect data corruption by
soft errors in the CRAM cells. This feature allows all CRAM contents to be read and
verified to match a configuration-computed CRC value. Soft errors are changes in a
CRAM’s bit state due to an ionizing particle.
The error detection capability continuously computes the CRC of the configured
CRAM bits and compares it with the pre-calculated CRC. If the CRCs match, there is
no error in the current configuration CRAM bits. The process of error detection
continues until the device is reset (by setting nCONFIG low).
As soon as the device transitions into user mode, you can enable the error detection
process if you enable the CRC error detection option. The internal 100-MHz
configuration oscillator is divided down by a factor of 2 to 256 (at powers of 2) to be
used as the clock source during the error detection process. Set the clock divide factor
in the option setting in the Quartus II software.
“Configuration Error Detection”
Chapter 15: SEU Mitigation in Stratix III Devices
© March 2010 Altera Corporation
and
Error Detection Fundamentals
“User Mode Error